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[2/9] memory: emif: setup LP settings on freq update

Message ID 1355123358-5273-3-git-send-email-lokeshvutla@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lokesh Vutla Dec. 10, 2012, 7:09 a.m. UTC 
From: Nishanth Menon <nm@ti.com>

Program the power management shadow register on freq update
else the concept of threshold frequencies dont really matter
as the system always uses the performance mode timing for LP
which is programmed in at init time.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 drivers/memory/emif.c |    5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
index 8589aba..69a480d 100644
--- a/drivers/memory/emif.c
+++ b/drivers/memory/emif.c
@@ -815,6 +815,11 @@  static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
 	writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
 	writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 
+	if (emif->lpmode != EMIF_LP_MODE_DISABLE) {
+		writel(regs->pwr_mgmt_ctrl_shdw,
+		       base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
+	}
+
 	/* Settings specific for EMIF4D5 */
 	if (emif->plat_data->ip_rev != EMIF_4D5)
 		return;