From patchwork Sun Dec 16 21:49:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Cans X-Patchwork-Id: 1885601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 263DADFAC4 for ; Sun, 16 Dec 2012 20:53:09 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TkLAG-0001Zl-P1; Sun, 16 Dec 2012 20:50:24 +0000 Received: from mail-wg0-f51.google.com ([74.125.82.51]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TkLAB-0001Yq-5O for linux-arm-kernel@lists.infradead.org; Sun, 16 Dec 2012 20:50:21 +0000 Received: by mail-wg0-f51.google.com with SMTP id gg4so2149110wgb.18 for ; Sun, 16 Dec 2012 12:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=vrIlfLQIFvbQIuRbX2O9nsC446f7gg10rhD22Yj4nus=; b=L9tXJprNeVvfDdu8dkOQFFYXW6rhygnXxyPxvYZi1tmdHL2Jy4S3VinbJTgY9ReevZ GroqZHKiHcPsPuhc5aW//ci5I6zo50+Y7nIuj1JIEzvPLXehu+4b7wJM/pp0Azeqec/b A/l+d7VtNhR+bkruO2Q1SLQKq0RhGGSPQcPqU+JbBXRquFAX6HFc4wlMNZXnE2pY25Nr zvhrS8eA8k+Gw9KUZXK8BA2ARBHIKXy+aQbM/cvZ4Qc9v4BFBIGDGHd72ggT6SmRxZ6X 41HmqpPOCkStlhWXxjRqJ/PjEXm0C2m9G1ZhuGmzbxXvxhxyspjJXwlzZs/8+1TpZz9s 4k5A== Received: by 10.194.238.226 with SMTP id vn2mr13358749wjc.23.1355691016618; Sun, 16 Dec 2012 12:50:16 -0800 (PST) Received: from localhost.localdomain (che78-4-88-174-199-71.fbx.proxad.net. [88.174.199.71]) by mx.google.com with ESMTPS id i2sm8242008wiw.3.2012.12.16.12.50.15 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 16 Dec 2012 12:50:15 -0800 (PST) From: Laurent Cans To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] Add apf51 basic support Date: Sun, 16 Dec 2012 22:49:51 +0100 Message-Id: <1355694591-7084-1-git-send-email-laurent.cans@gmail.com> X-Mailer: git-send-email 1.7.10.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121216_155019_446679_555AF909 X-CRM114-Status: GOOD ( 11.95 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.51 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (laurent.cans[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: s.hauer@pengutronix.de, Laurent Cans , Gwenhael Goavec-Merou X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Signed-off-by: Laurent Cans Signed-off-by: Gwenhael Goavec-Merou --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx51-apf51.dts | 68 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx51.dtsi | 30 ++++++++++++++++ 3 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx51-apf51.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9f..8600cdf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -45,7 +45,8 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-xp-db.dtb -dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ +dtb-$(CONFIG_ARCH_MXC) += imx51-apf51.dtb \ + imx51-babbage.dtb \ imx53-ard.dtb \ imx53-evk.dtb \ imx53-qsb.dtb \ diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts new file mode 100644 index 0000000..c7cdafa --- /dev/null +++ b/arch/arm/boot/dts/imx51-apf51.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Laurent Cans + * + * Based on mx51-babbage.dts + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx51.dtsi" + +/ { + model = "Armadeus Systems APF51 Board"; + compatible = "fsl,imx51-apf51", "fsl,imx51"; + memory { + reg = <0x90000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <33554432>; + }; + }; + soc { + aips@70000000 { /* aips-1 */ + spba@70000000 { + uart3: serial@7000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2>; + status = "okay"; + }; + }; + }; + aips@80000000 { /* aips-2 */ + nand0: nand@83fdb000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; + }; + + ethernet@83fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_2>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio3 0 0>; + phy-reset-duration = <1>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 75d069f..0de37bd 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -248,6 +248,29 @@ 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ >; }; + + pinctrl_fec_2: fecgrp-2 { + fsl,pins = < + 589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */ + 592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */ + 594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */ + 596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */ + 598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */ + 602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */ + 604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */ + 609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */ + 618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */ + 623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */ + 628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */ + 634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */ + 639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */ + 644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */ + 649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */ + 653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */ + 657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */ + 662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */ + >; + }; }; ecspi1 { @@ -324,6 +347,13 @@ 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ >; }; + + pinctrl_uart3_2: uart3grp-2 { + fsl,pins = < + 434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */ + 430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */ + >; + }; }; };