From patchwork Thu Dec 20 09:44:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1899171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 5792A3FC64 for ; Thu, 20 Dec 2012 09:49:12 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tlchu-0006iK-K1; Thu, 20 Dec 2012 09:46:26 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tlche-0006dE-GX for linux-arm-kernel@lists.infradead.org; Thu, 20 Dec 2012 09:46:12 +0000 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Thu, 20 Dec 2012 01:45:33 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Thu, 20 Dec 2012 01:45:52 -0800 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Thu, 20 Dec 2012 01:45:52 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Thu, 20 Dec 2012 01:45:52 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 20 Dec 2012 01:46:09 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id qBK9inJ8013509; Thu, 20 Dec 2012 01:45:48 -0800 (PST) From: Hiroshi Doyu To: Subject: [PATCH 5/9] clocksource: tegra: Enable ARM arch_timer with TSC Date: Thu, 20 Dec 2012 11:44:03 +0200 Message-ID: <1355996654-6579-6-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355996654-6579-1-git-send-email-hdoyu@nvidia.com> References: <1355996654-6579-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121220_044611_705010_474B7D4C X-CRM114-Status: GOOD ( 18.60 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Andrew Lunn , Russell King , Jason Cooper , Stephen Warren , John Stultz , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Rob Landley , Olof Johansson , Thomas Gleixner , Shawn Guo , Jean-Christophe PLAGNIOL-VILLARD , linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add platform enabler for ARM arch_timer(TSC). TSC is more fine grained timer than TMR0. If it's available, it will be used for clock source and sched_clock. Otherwise, TMR0 is used. In any case TMR0 is necessary for clock event. Signed-off-by: Hiroshi Doyu --- .../bindings/arm/tegra/nvidia,tegra114-tsc.txt | 11 ++++ drivers/clocksource/tegra20_timer.c | 64 +++++++++++++++++++- 2 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt new file mode 100644 index 0000000..9de936a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-tsc.txt @@ -0,0 +1,11 @@ +NVIDIA Tegra Timer Stamp Counter(TSC) + +Required properties: +- compatible : "nvidia,tegra114-tsc +- reg : Should contain 1 register ranges(address and length) + +Example: + tsc { + compatible = "nvidia,tegra114-tsc"; + reg = <0x700f0000 0x20000>; + }; diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index 1d25de8..285a6f1 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -30,6 +30,7 @@ #include #include #include +#include #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c @@ -271,10 +272,71 @@ static void __init tegra20_init_tmr(void) clockevents_register_device(&tegra_clockevent); } +#define TSC_CNTCR 0 /* TSC control registers */ +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#define TSC_CNTCV0 0x8 /* TSC counter (LSW) */ +#define TSC_CNTCV1 0xc /* TSC counter (MSW) */ +#define TSC_CNTFID0 0x20 /* TSC freq id 0 */ + +static const struct of_device_id tegra_tsc_match[] __initconst = { + { .compatible = "nvidia,tegra114-tsc" }, + {} +}; + +static int tegra_arch_timer_init(void) +{ + int err; + struct device_node *np; + struct clk *clk; + void __iomem *tsc_base; + u32 freq, val; + + np = of_find_matching_node(NULL, tegra_tsc_match); + if (!np) + return -ENODEV; + + tsc_base = of_iomap(np, 0); + if (!tsc_base) + return -ENODEV; + + clk = clk_get_sys("clk_m", NULL); + if (IS_ERR(clk)) { + freq = 12000000; + pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); + } else { + freq = clk_get_rate(clk); + clk_put(clk); + } + writel_relaxed(freq, tsc_base + TSC_CNTFID0); + + /* CNTFRQ */ + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); + asm("mrc p15, 0, %0, c14, c0, 0\n" : "=r" (val)); + BUG_ON(val != freq); + + val = readl_relaxed(tsc_base + TSC_CNTCR); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel_relaxed(val, tsc_base + TSC_CNTCR); + + err = arch_timer_of_register(); + if (!err) + err = arch_timer_sched_clock_init(); + if (err) + pr_err("Failed to register ARM arch_timer(TSC)\n"); + return err; +} + static void __init tegra20_init_timer(void) { + int err = -ENODEV; + tegra20_init_tmr(); - setup_sched_clock(tegra_read_sched_clock, 32, 1000000); + if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) + err = tegra_arch_timer_init(); + if (err) + setup_sched_clock(tegra_read_sched_clock, 32, 1000000); tegra20_init_rtc(); #ifdef CONFIG_HAVE_ARM_TWD twd_local_timer_of_register();