From patchwork Fri Dec 21 09:45:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1902711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 630E240076 for ; Fri, 21 Dec 2012 09:49:39 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TlzBo-0005yS-F6; Fri, 21 Dec 2012 09:46:48 +0000 Received: from mail-pa0-f44.google.com ([209.85.220.44]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TlzAq-0005hL-Am for linux-arm-kernel@lists.infradead.org; Fri, 21 Dec 2012 09:45:50 +0000 Received: by mail-pa0-f44.google.com with SMTP id hz11so2712416pad.3 for ; Fri, 21 Dec 2012 01:45:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=iarbu+dTFBMlpVV9YwXq2C9lAeaJcjFY81PVPvoMOH4=; b=ZKRT+YUsOElnO7U+TDXPWSvrS1Qq1py5B5VOZn5bKyBWRNrSSKJRlJHo3gAbeB4R/8 p20hwdOzPMyTdWLqb+Ws/Y28e2aL/wCiMKfnkvqZ9QBpKfJsskujWDdDCRyfPKa1M3JA moxB6vcy0ZkJ0638OAEnkRFFCWkXmV0cBBHzsfacC20zdhTuvcTYpXu/Gzpfj/b4QVaE ZnNilm8Q7hHzfeI9VJD9lLKocl2Yw8VbbBl6ggnQHY14rj5hBrOA9y1T3ykcK+W9+hz/ GTlwmfW+7+dkBAF7A9PFFZ/6iyK1Tx8cZQ6w22TRBZkrcYjyhyPpQ0VAVxxSbIna9uwb 7xlg== X-Received: by 10.68.192.70 with SMTP id he6mr38442528pbc.142.1356083146768; Fri, 21 Dec 2012 01:45:46 -0800 (PST) Received: from localhost.localdomain ([116.224.148.148]) by mx.google.com with ESMTPS id t5sm7104258paw.20.2012.12.21.01.45.43 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Dec 2012 01:45:46 -0800 (PST) From: Haojian Zhuang To: linus.walleij@linaro.org, tony@atomide.com, linux-arm-kernel@lists.infradead.org, swarren@nvidia.com Subject: [PATCH v6 5/8] document: devicetree: bind pinconf with pin single Date: Fri, 21 Dec 2012 17:45:15 +0800 Message-Id: <1356083118-18857-6-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1356083118-18857-1-git-send-email-haojian.zhuang@linaro.org> References: <1356083118-18857-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQmc8xV20zz+35Wb8FSKfIB1CAx3AwEcB8z+YGavIFYrhEFxUWs5OzAcKBunxicz2JTNTlX1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121221_044548_562185_A9C2759B X-CRM114-Status: GOOD ( 15.91 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.44 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Haojian Zhuang Add comments with pinconf & gpio range in the document of pinctrl-single. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 82 +++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45..7d1d4b2 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -1,7 +1,9 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" +- compatible : "pinctrl-single" or "pinconf-single". + "pinctrl-single" means that pinconf isn't supported. + "pinconf-single" means that generic pinconf is supported. - reg : offset and length of the register set for the mux registers @@ -14,9 +16,31 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored + - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,power-source : array of value that are used to configure + power source in the pinmux register. They're value of power source field + and power source mask. + + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + +- pinctrl-single,bias : array of value that are used to configure the input + bias in the pinmux register. They're value of bias field, bias mask, + bias disable value, bias pull down value & bias pull up value. + + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. They're value of input schmitt field, + mask, & disable value. + + /* input schmitt value, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -42,6 +66,24 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. + +Optional sub-node: In case some pins could be configured as GPIO in the pinmux +register, those pins could be defined as a GPIO range. The sub-node should +be defined in .dtsi files of those silicons. + +Required properties in sub-node: +- reg : offset and length of the GPIO range sub-node. + +- pinctrl-single,gpio : array of GPIO base number in the range and the GPIO + function in the pinmux register. + + range0: { + /* GPIO0 ~ GPIO54 */ + reg = <0xd401e0dc 55>; + pinctrl-single,gpio = <0 0>; + }; + + Example: /* SoC common file */ @@ -76,6 +118,26 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux@d401e000 { + compatible = "pinconf-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + range0: range@d401e0dc { + /* GPIO0 ~ GPIO54 */ + reg = <0xd401e0dc 0xdc>; + /* gpio base & gpio func */ + pinctrl-single,gpio = <0 0>; + }; +}; + + /* board specific .dts file */ &pmx_core { @@ -96,6 +158,19 @@ control_devconf0: pinmux@48002274 { >; }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x198 0x6 /* GPIO47_UART1_RXD */ + 0x19c 0x6 /* GPIO48_UART1_TXD */ + >; + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + /* input schmitt, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + /* map uart2 pins */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < @@ -122,6 +197,11 @@ control_devconf0: pinmux@48002274 { }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>;