From patchwork Wed Jan 9 20:43:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1955611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C000A3FD40 for ; Wed, 9 Jan 2013 20:52:15 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tt2Yv-00063V-6n; Wed, 09 Jan 2013 20:47:49 +0000 Received: from moutng.kundenserver.de ([212.227.17.9]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tt2VA-00049t-3r for linux-arm-kernel@lists.infradead.org; Wed, 09 Jan 2013 20:43:58 +0000 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0Llco8-1TJhk52WKu-00ZN1J; Wed, 09 Jan 2013 21:43:26 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id C44832A2813C; Wed, 9 Jan 2013 21:43:24 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Rt9rxA8JPyKA; Wed, 9 Jan 2013 21:43:23 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id DD47A2A2814D; Wed, 9 Jan 2013 21:43:16 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id 2C4E9100423; Wed, 9 Jan 2013 21:43:12 +0100 (CET) From: Thierry Reding To: linux-tegra@vger.kernel.org Subject: [PATCH 08/14] ARM: tegra: Move tegra_pcie_xclk_clamp() to PMC Date: Wed, 9 Jan 2013 21:43:08 +0100 Message-Id: <1357764194-12677-9-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1357764194-12677-1-git-send-email-thierry.reding@avionic-design.de> References: <1357764194-12677-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:Lbjft7eKNL9gZqkdzuccvD3vXYwSi5/XMvu5HcvJLqL aZhyrlUBH1+fIuKy6cCRwIj96wFsEHxnhacGOYztJK8KhH2X0z j+CF0KPDZ45/svbxUWg4R21Q62FbGFsfjv4vNcOVVZAx5gLuVK 2UlPDDtPhlMnybm29LL97PPPgQ0i24LNaOEIG7+envDWiLGKmd KW+kCcNqfEcL8m6BUImvIxAFUV0QCv/EuepWYSr8v8Eq+zql2c VsSnB4DEcS+a5O8BfZaeP0tdf6tWV+mefqLc5Y5XRJ8mmnWffO LYlI/4UntKciuX50ABwxmqFAXHpEpuIKbbmpRlBZv8EVRex5R/ 6wCl2Z+7QOVmZFZtCdce8Tq+3PZN+9o3w1Ao1ORB/PpdrxhQbU HXH5tEPjxygPa+eza6N6dR+Ifi+MNLl0scfhJqK+qUmbndt6ZV qwHmi X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130109_154356_531316_125CDB49 X-CRM114-Status: GOOD ( 14.09 ) X-Spam-Score: 1.1 (+) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (1.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.17.9 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Thomas Petazzoni , Jason Gunthorpe , Russell King , Arnd Bergmann , Stephen Warren , linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Bjorn Helgaas , Andrew Murray , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The PMC code already accesses to PMC registers so it makes sense to move this function there as well. While at it, rename the function to tegra_pmc_pcie_xclk_clamp() for consistency. Signed-off-by: Thierry Reding Acked-by: Stephen Warren --- Changes in v3: - none Changes in v2: - none --- arch/arm/mach-tegra/pcie.c | 30 ++++-------------------------- arch/arm/mach-tegra/pmc.c | 16 ++++++++++++++++ arch/arm/mach-tegra/pmc.h | 1 + 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index bffcd64..c2d55f8 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -42,6 +42,7 @@ #include "board.h" #include "iomap.h" +#include "pmc.h" /* Hack - need to parse this from DT */ #define INT_PCIE_INTR 130 @@ -148,17 +149,6 @@ #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) -/* PMC access is required for PCIE xclk (un)clamping */ -#define PMC_SCRATCH42 0x144 -#define PMC_SCRATCH42_PCX_CLAMP (1 << 0) - -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); - -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) - /* * Tegra2 defines 1GB in the AXI address map for PCIe. * @@ -640,18 +630,6 @@ static int tegra_pcie_enable_controller(void) return 0; } -static void tegra_pcie_xclk_clamp(bool clamp) -{ - u32 reg; - - reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; - - if (clamp) - reg |= PMC_SCRATCH42_PCX_CLAMP; - - pmc_writel(reg, PMC_SCRATCH42); -} - static void tegra_pcie_power_off(void) { tegra_periph_reset_assert(tegra_pcie.pcie_xclk); @@ -659,7 +637,7 @@ static void tegra_pcie_power_off(void) tegra_periph_reset_assert(tegra_pcie.pex_clk); tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); - tegra_pcie_xclk_clamp(true); + tegra_pmc_pcie_xclk_clamp(true); } static int tegra_pcie_power_regate(void) @@ -668,7 +646,7 @@ static int tegra_pcie_power_regate(void) tegra_pcie_power_off(); - tegra_pcie_xclk_clamp(true); + tegra_pmc_pcie_xclk_clamp(true); tegra_periph_reset_assert(tegra_pcie.pcie_xclk); tegra_periph_reset_assert(tegra_pcie.afi_clk); @@ -682,7 +660,7 @@ static int tegra_pcie_power_regate(void) tegra_periph_reset_deassert(tegra_pcie.afi_clk); - tegra_pcie_xclk_clamp(false); + tegra_pmc_pcie_xclk_clamp(false); clk_prepare_enable(tegra_pcie.afi_clk); clk_prepare_enable(tegra_pcie.pex_clk); diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index d4fdb5f..a335a93 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -24,6 +24,10 @@ #define PMC_CTRL 0x0 #define PMC_CTRL_INTR_LOW (1 << 17) +/* PMC access is required for PCIE xclk (un)clamping */ +#define PMC_SCRATCH42 0x144 +#define PMC_SCRATCH42_PCX_CLAMP (1 << 0) + static inline u32 tegra_pmc_readl(u32 reg) { return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg)); @@ -74,3 +78,15 @@ void __init tegra_pmc_init(void) val &= ~PMC_CTRL_INTR_LOW; tegra_pmc_writel(val, PMC_CTRL); } + +void tegra_pmc_pcie_xclk_clamp(bool clamp) +{ + u32 reg; + + reg = tegra_pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; + + if (clamp) + reg |= PMC_SCRATCH42_PCX_CLAMP; + + tegra_pmc_writel(reg, PMC_SCRATCH42); +} diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index 8995ee4..2631c9a 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h @@ -19,5 +19,6 @@ #define __MACH_TEGRA_PMC_H void tegra_pmc_init(void); +void tegra_pmc_pcie_xclk_clamp(bool clamp); #endif