From patchwork Tue Jan 15 06:08:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 1974871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 67C413FE1B for ; Tue, 15 Jan 2013 06:12:17 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tuzhv-0008RN-Da; Tue, 15 Jan 2013 06:09:11 +0000 Received: from va3ehsobe004.messaging.microsoft.com ([216.32.180.14] helo=va3outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tuzhq-0008Qt-Fm for linux-arm-kernel@lists.infradead.org; Tue, 15 Jan 2013 06:09:08 +0000 Received: from mail9-va3-R.bigfish.com (10.7.14.240) by VA3EHSOBE014.bigfish.com (10.7.40.64) with Microsoft SMTP Server id 14.1.225.23; Tue, 15 Jan 2013 06:09:05 +0000 Received: from mail9-va3 (localhost [127.0.0.1]) by mail9-va3-R.bigfish.com (Postfix) with ESMTP id 50302E02CA; Tue, 15 Jan 2013 06:09:05 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h1155h) Received: from mail9-va3 (localhost.localdomain [127.0.0.1]) by mail9-va3 (MessageSwitch) id 1358230143290141_5754; Tue, 15 Jan 2013 06:09:03 +0000 (UTC) Received: from VA3EHSMHS045.bigfish.com (unknown [10.7.14.244]) by mail9-va3.bigfish.com (Postfix) with ESMTP id 05EF12C005E; Tue, 15 Jan 2013 06:09:01 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS045.bigfish.com (10.7.99.55) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 15 Jan 2013 06:09:01 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.318.3; Tue, 15 Jan 2013 06:09:00 +0000 Received: from localhost.localdomain (nchen-desktop.ap.freescale.net [10.192.242.40]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r0F68cEJ000665; Mon, 14 Jan 2013 23:08:54 -0700 From: Peter Chen To: , , , , , , Subject: [PATCH v2 2/4] usb: mxs-phy: change clock usage for i.mx6q Date: Tue, 15 Jan 2013 14:08:35 +0800 Message-ID: <1358230117-19443-2-git-send-email-peter.chen@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1358230117-19443-1-git-send-email-peter.chen@freescale.com> References: <1358230117-19443-1-git-send-email-peter.chen@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130115_010906_732007_27B81E9D X-CRM114-Status: GOOD ( 18.81 ) X-Spam-Score: 0.4 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.14 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: marex@denx.de, m.grzeschik@pengutronix.de, linux-doc@vger.kernel.org, matt@genesi-usa.com, devicetree-discuss@lists.ozlabs.org, linux-usb@vger.kernel.org, mkl@pengutronix.de, maxime.ripard@free-electrons.com, festevam@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org For mxs-phy user i.mx6q, the PHY's clock is controlled by hardware automatically, the software only needs to enable it at probe, disable it at remove. But other mxs-phy users need to control that clock runtime, so we hardcode clk on/off, and give a reserved bit for clk on/off at clk code for i.mx6q. Signed-off-by: Peter Chen --- Changes for v2: - Only control gate bit for phy clk control - Only open the gate at probe, and close the gate at remove Documentation/devicetree/bindings/usb/mxs-phy.txt | 2 + arch/arm/boot/dts/imx6q.dtsi | 2 + drivers/usb/otg/mxs-phy.c | 61 +++++++++++++++++++++ 3 files changed, 65 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt index 5835b27..384e700 100644 --- a/Documentation/devicetree/bindings/usb/mxs-phy.txt +++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt @@ -4,10 +4,12 @@ Required properties: - compatible: Should be "fsl,imx23-usbphy" - reg: Should contain registers location and length - interrupts: Should contain phy interrupt +- The reg offset for PHY clock at anatop Example: usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; + anatop-phy-reg-offset = <0x10>; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d6265ca..1517e93 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -519,6 +519,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; clocks = <&clks 182>; + anatop-phy-reg-offset = <0x10>; }; usbphy2: usbphy@020ca000 { @@ -526,6 +527,7 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; clocks = <&clks 183>; + anatop-phy-reg-offset = <0x20>; }; snvs@020cc000 { diff --git a/drivers/usb/otg/mxs-phy.c b/drivers/usb/otg/mxs-phy.c index 7630272..49727dd 100644 --- a/drivers/usb/otg/mxs-phy.c +++ b/drivers/usb/otg/mxs-phy.c @@ -20,6 +20,9 @@ #include #include #include +#include +#include +#include #define DRIVER_NAME "mxs_phy" @@ -34,6 +37,11 @@ #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) +#define CTRL_SET 0x4 +#define CTRL_CLR 0x8 + +#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6) + struct mxs_phy { struct usb_phy phy; struct clk *clk; @@ -108,6 +116,7 @@ static int mxs_phy_probe(struct platform_device *pdev) void __iomem *base; struct clk *clk; struct mxs_phy *mxs_phy; + struct regmap *anatop; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -146,11 +155,63 @@ static int mxs_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, &mxs_phy->phy); + /* + * At mx6x, USB PHY PLL and its output gate is controlled by hardware. + * It just needs to open the gate at init, if the usb device is + * in suspend, it will close related PLL automatically without + * the gate is on or off. + */ + + anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); + + if (!IS_ERR(anatop)) { + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + u32 phy_reg_offset; + int ret; + + ret = of_property_read_u32(np, "anatop-phy-reg-offset", + &phy_reg_offset); + if (ret) { + dev_err(dev, "no anatop-phy-reg-offset property set\n"); + return -EINVAL; + } + + regmap_write(anatop, phy_reg_offset + CTRL_SET, + BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS); + } else { + pr_warn("failed to find fsl,imx6q-anatop regmap\n"); + } + return 0; } static int mxs_phy_remove(struct platform_device *pdev) { + struct regmap *anatop; + + /* close the clock gate for USB PHY */ + anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); + + if (!IS_ERR(anatop)) { + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + u32 phy_reg_offset; + int ret; + + ret = of_property_read_u32(np, "anatop-phy-reg-offset", + &phy_reg_offset); + if (ret) { + dev_err(dev, "no anatop-phy-reg-offset property set\n"); + return -EINVAL; + } + + regmap_write(anatop, phy_reg_offset + CTRL_CLR, + BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS); + } else { + pr_warn("failed to find fsl,imx6q-anatop regmap\n"); + } + platform_set_drvdata(pdev, NULL); return 0;