From patchwork Tue Jan 15 08:13:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 2073611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id CD671DF2E5 for ; Thu, 31 Jan 2013 12:59:29 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U0thQ-0006FH-RP; Thu, 31 Jan 2013 12:57:04 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tv1ei-0006mj-OX for linux-arm-kernel@lists.infradead.org; Tue, 15 Jan 2013 08:14:01 +0000 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Tue, 15 Jan 2013 00:18:06 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Tue, 15 Jan 2013 00:12:53 -0800 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Tue, 15 Jan 2013 00:12:53 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Tue, 15 Jan 2013 00:13:59 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Tue, 15 Jan 2013 00:13:59 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r0F8Dn39018770; Tue, 15 Jan 2013 00:13:58 -0800 (PST) From: Hiroshi Doyu To: Subject: [v3 4/9] ARM: Add API to detect SCU base address from CP15 Date: Tue, 15 Jan 2013 10:13:13 +0200 Message-ID: <1358237598-32413-5-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> References: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130115_031401_014522_DEA6E9BE X-CRM114-Status: GOOD ( 11.20 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-Mailman-Approved-At: Thu, 31 Jan 2013 07:54:31 -0500 Cc: lorenzo.pieralisi@arm.com, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add API to detect SCU base address from CP15. Signed-off-by: Hiroshi Doyu --- arch/arm/include/asm/smp_scu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 4eb6d00..f619eef 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -6,6 +6,23 @@ #define SCU_PM_POWEROFF 3 #ifndef __ASSEMBLER__ + +#include + +static inline phys_addr_t scu_get_base(void) +{ + phys_addr_t pa; + unsigned long part_number = read_cpuid_part_number(); + + switch (part_number) { + case ARM_CPU_PART_CORTEX_A9: + /* Get SCU physical base */ + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); + return pa; + default: + return 0; + } +} unsigned int scu_get_core_count(void __iomem *); void scu_enable(void __iomem *); int scu_power_mode(void __iomem *, unsigned int);