From patchwork Tue Jan 15 16:48:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 1979651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id C16F7DF264 for ; Tue, 15 Jan 2013 16:52:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tv9hW-0004wq-Bb; Tue, 15 Jan 2013 16:49:26 +0000 Received: from mail-bk0-f42.google.com ([209.85.214.42]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tv9gs-0004p0-BX for linux-arm-kernel@lists.infradead.org; Tue, 15 Jan 2013 16:48:47 +0000 Received: by mail-bk0-f42.google.com with SMTP id ji2so200109bkc.29 for ; Tue, 15 Jan 2013 08:48:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=IpHYRW8ok92LsGG0roW0AHfCd7uB6v0b6OX+eqkFgwM=; b=dkXkyBLaH17WYE5xk8LHqZ279WC4g9FxH4lfObBzE8VFUdc0P4auJFoDwcjVjYS9/3 WMwaB8wj/3GFmn10CPZ3b/5VbyWhtqrWfBx9Q4nO0bUYjbvFYCjiWa74eY1uAH0ERvSR F6pbuo3T+Mkop4u7c63gQQlH5llX3DS+fEoAS0Sw/GUkaFI/543ACvmI44Uv+U//ZCGL CsZCsVm2XMOrnkgeN50avTtkAxtLFRd05Vgfxc+vBB4g4L5hfG7sPerGIqGHPTbt/5lh PM9E1CjA1pBKmhQOBOFS5w2lGn9zJw87pIPVsdCDVzZZXq6RiqjzvIAtm2mKVI3luLfI fukQ== X-Received: by 10.204.7.145 with SMTP id d17mr40647312bkd.84.1358268524069; Tue, 15 Jan 2013 08:48:44 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id 18sm13338796bkv.0.2013.01.15.08.48.42 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Jan 2013 08:48:43 -0800 (PST) From: Dave Martin To: Nicolas Pitre Subject: [RFC PATCH 3/4] ARM: bL_entry: Match memory barriers to architectural requirements Date: Tue, 15 Jan 2013 16:48:17 +0000 Message-Id: <1358268498-8086-4-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1358268498-8086-1-git-send-email-dave.martin@linaro.org> References: <1358268498-8086-1-git-send-email-dave.martin@linaro.org> X-Gm-Message-State: ALoCoQlgSus5O5ZIMzSuYjokwmm2n1JCWy64D96tMRHIAMegk+SA5+vTGdUOjdIgYU8N/Bb42nE9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130115_114846_601181_89736576 X-CRM114-Status: GOOD ( 12.47 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.42 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Achin Gupta , Will Deacon , Dave Martin , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org For architectural correctness even Strongly-Ordered memory accesses require barriers in order to guarantee that multiple CPUs have a coherent view of the ordering of memory accesses. Virtually everything done by this early code is done via explicit memory access only, so DSBs are seldom required. Existing barriers are demoted to DMB, except where a DSB is needed to synchronise non-memory signalling (i.e., before a SEV). If a particular platform performs cache maintenance in its power_up_setup function, it should force it to complete explicitly including a DSB, instead of relying on the bL_head framework code to do it. Some additional DMBs are added to ensure all the memory ordering properties required by the race avoidance algorithm. DMBs are also moved out of loops, and for clarity some are moved so that most directly follow the memory operation which needs to be synchronised. The setting of a CPU's bL_entry_vectors[] entry is also required to act as a synchronisation point, so a DMB is added after checking that entry to ensure that other CPUs do not observe gated operations leaking across the opening of the gate. Signed-off-by: Dave Martin --- arch/arm/common/bL_head.S | 21 +++++++++++---------- 1 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/common/bL_head.S b/arch/arm/common/bL_head.S index fd71ff6..a4a20e5 100644 --- a/arch/arm/common/bL_head.S +++ b/arch/arm/common/bL_head.S @@ -87,8 +87,7 @@ ENTRY(bL_entry_point) mov r5, #BL_SYNC_CPU_SIZE mla r5, r9, r5, r8 @ r5 = bL_sync cpu address strb r0, [r5] - - dsb + dmb @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN @ state, because there is at least one active CPU (this CPU). @@ -97,7 +96,7 @@ ENTRY(bL_entry_point) mla r11, r0, r10, r11 @ r11 = cluster first man lock mov r0, r11 mov r1, r9 @ cpu - bl vlock_trylock + bl vlock_trylock @ implies DSB cmp r0, #0 @ failed to get the lock? bne cluster_setup_wait @ wait for cluster setup if so @@ -115,11 +114,12 @@ cluster_setup: @ Wait for any previously-pending cluster teardown operations to abort @ or complete: - dsb - ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER] + dmb +0: ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER] cmp r0, #CLUSTER_GOING_DOWN wfeeq - beq cluster_setup + beq 0b + dmb @ If the outbound gave up before teardown started, skip cluster setup: @@ -131,8 +131,8 @@ cluster_setup: cmp r7, #0 mov r0, #1 @ second (cluster) affinity level blxne r7 @ Call power_up_setup if defined + dmb - dsb mov r0, #CLUSTER_UP strb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER] dsb @@ -146,11 +146,11 @@ cluster_setup_leave: @ In the contended case, non-first men wait here for cluster setup @ to complete: cluster_setup_wait: - dsb ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER] cmp r0, #CLUSTER_UP wfene bne cluster_setup_wait + dmb cluster_setup_complete: @ If a platform-specific CPU setup hook is needed, it is @@ -162,13 +162,14 @@ cluster_setup_complete: @ Mark the CPU as up: - dsb + dmb mov r0, #CPU_UP strb r0, [r5] + dmb bL_entry_gated: - dsb ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector + dmb cmp r5, #0 wfeeq beq bL_entry_gated