From patchwork Wed Jan 16 16:13:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Zabel X-Patchwork-Id: 1991031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 993A8DF2A2 for ; Wed, 16 Jan 2013 16:18:42 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TvVdc-0007fL-3c; Wed, 16 Jan 2013 16:14:52 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TvVc7-0007Dw-3t for linux-arm-kernel@lists.infradead.org; Wed, 16 Jan 2013 16:13:27 +0000 Received: from dude.hi.pengutronix.de ([10.1.0.7] helo=dude.pengutronix.de) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1TvVc1-0006F4-Dt; Wed, 16 Jan 2013 17:13:13 +0100 From: Philipp Zabel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/7] ARM i.MX5: Add System Reset Controller (SRC) support for i.MX51 and i.MX53 Date: Wed, 16 Jan 2013 17:13:06 +0100 Message-Id: <1358352787-15441-7-git-send-email-p.zabel@pengutronix.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358352787-15441-1-git-send-email-p.zabel@pengutronix.de> References: <1358352787-15441-1-git-send-email-p.zabel@pengutronix.de> X-SA-Exim-Connect-IP: 10.1.0.7 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130116_111320_917272_FFF2A3B1 X-CRM114-Status: GOOD ( 14.44 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Marek Vasut , Fabio Estevam , Mike Turquette , Philipp Zabel , Stephen Warren , Sascha Hauer , kernel@pengutronix.de, Shawn Guo , devicetree-discuss@lists.ozlabs.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by: Philipp Zabel --- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/common.h | 3 ++- arch/arm/mach-imx/mach-imx6q.c | 2 +- arch/arm/mach-imx/mm-imx5.c | 2 ++ arch/arm/mach-imx/src.c | 14 +++++++++++++- 5 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3e628fd..d7924e5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -829,6 +829,7 @@ config SOC_IMX53 select ARCH_MX53 select HAVE_CAN_FLEXCAN if CAN select IMX_HAVE_PLATFORM_IMX2_WDT + select HAVE_IMX_SRC select PINCTRL select PINCTRL_IMX53 select SOC_IMX5 diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 7191ab4..f36be3c 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -133,7 +133,8 @@ static inline void imx_smp_prepare(void) {} #endif extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); -extern void imx_src_init(void); +extern void imx5_src_init(void); +extern void imx6q_src_init(void); extern void imx_src_prepare_restart(void); extern void imx_gpc_init(void); extern void imx_gpc_pre_suspend(void); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index cd277a0..b1e076c 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -229,7 +229,7 @@ static const struct of_device_id imx6q_irq_match[] __initconst = { static void __init imx6q_init_irq(void) { l2x0_of_init(0, ~0UL); - imx_src_init(); + imx6q_src_init(); imx_gpc_init(); of_irq_init(imx6q_irq_match); } diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 79d71cf..53f87be 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -106,6 +106,7 @@ void __init imx51_init_early(void) mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); + imx5_src_init(); } void __init imx53_init_early(void) @@ -113,6 +114,7 @@ void __init imx53_init_early(void) mxc_set_cpu_type(MXC_CPU_MX53); mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); + imx5_src_init(); } void __init mx50_init_irq(void) diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 41687c6..e350250 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -125,7 +125,19 @@ void imx_src_prepare_restart(void) writel_relaxed(0, src_base + SRC_GPR1); } -void __init imx_src_init(void) +void __init imx5_src_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx5-src"); + src_base = of_iomap(np, 0); + WARN_ON(!src_base); + + imx_reset_controller.of_node = np; + reset_controller_register(&imx_reset_controller); +} + +void __init imx6q_src_init(void) { struct device_node *np; u32 val;