| Message ID | 1358352787-15441-8-git-send-email-p.zabel@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 01/16/2013 09:13 AM, Philipp Zabel wrote: > Also, link SRC to IPU via phandle. Aside from the comments I already made, the series, Reviewed-by: Stephen Warren <swarren@nvidia.com> although I'm not 100% sure if the ordering of patches maintains a working i.MX build all the time? Does "git bisect" work across the series? Who would merge these patches?
On Wed, Jan 16, 2013 at 03:19:44PM -0700, Stephen Warren wrote: > On 01/16/2013 09:13 AM, Philipp Zabel wrote: > > Also, link SRC to IPU via phandle. > > Aside from the comments I already made, the series, > Reviewed-by: Stephen Warren <swarren@nvidia.com> > > although I'm not 100% sure if the ordering of patches maintains a > working i.MX build all the time? Does "git bisect" work across the series? > > Who would merge these patches? I would assume IMX --> arm-soc --> mainline? Philipp, please copy arm-soc folks (Arnd and Olof) on the next post, so that they can get a chance to review this tiny reset subsystem. Shawn
Am Mittwoch, den 16.01.2013, 15:19 -0700 schrieb Stephen Warren: > On 01/16/2013 09:13 AM, Philipp Zabel wrote: > > Also, link SRC to IPU via phandle. > > Aside from the comments I already made, the series, > Reviewed-by: Stephen Warren <swarren@nvidia.com> Thank you. > although I'm not 100% sure if the ordering of patches maintains a > working i.MX build all the time? Does "git bisect" work across the series? Since IPU probing doesn't succeed if device_reset() fails, the IPU patch needs to be ordered after the i.MX5 patches. On the other hand, should device_reset() fail at all if no reset controller was specified in the device tree? regards Philipp
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 1f5d45e..1ff0adf 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -67,6 +67,7 @@ compatible = "fsl,imx51-ipu"; reg = <0x40000000 0x20000000>; interrupts = <11 10>; + resets = <&src 2>; }; aips@70000000 { /* AIPS1 */ @@ -448,6 +449,12 @@ status = "disabled"; }; + src: src@73fd0000 { + compatible = "fsl,imx5-src"; + reg = <0x73fd0000 0x4000>; + #reset-cells = <1>; + }; + clks: ccm@73fd4000{ compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index edc3f1e..088dc49 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -72,6 +72,7 @@ compatible = "fsl,imx53-ipu"; reg = <0x18000000 0x080000000>; interrupts = <11 10>; + resets = <&src 2>; }; aips@50000000 { /* AIPS1 */ @@ -497,6 +498,12 @@ status = "disabled"; }; + src: src@53fd0000 { + compatible = "fsl,imx5-src"; + reg = <0x53fd0000 0x4000>; + #reset-cells = <1>; + }; + clks: ccm@53fd4000{ compatible = "fsl,imx53-ccm"; reg = <0x53fd4000 0x4000>;
Also, link SRC to IPU via phandle. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- arch/arm/boot/dts/imx51.dtsi | 7 +++++++ arch/arm/boot/dts/imx53.dtsi | 7 +++++++ 2 files changed, 14 insertions(+)