From patchwork Fri Jan 18 07:19:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Bedia X-Patchwork-Id: 1999631 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id E17A0DF2F2 for ; Fri, 18 Jan 2013 07:24:08 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tw6Gc-0000rV-Sw; Fri, 18 Jan 2013 07:21:35 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tw6Eu-0008Vn-Vx for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2013 07:19:54 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0I7Jjb0002905; Fri, 18 Jan 2013 01:19:46 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0I7JfU4028821; Fri, 18 Jan 2013 12:49:45 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Fri, 18 Jan 2013 12:49:42 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0I7JbaK026026; Fri, 18 Jan 2013 12:49:42 +0530 From: Vaibhav Bedia To: , , Subject: [PATCH 9/9] ARM: OMAP2+: AM33XX: control: Add some control module registers and APIs Date: Fri, 18 Jan 2013 12:49:29 +0530 Message-ID: <1358493569-17142-10-git-send-email-vaibhav.bedia@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com> References: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130118_021949_281788_521D67AA X-CRM114-Status: GOOD ( 10.83 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.40 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: khilman@deeprootsystems.com, linux-omap@vger.kernel.org, santosh.shilimkar@ti.com, Vaibhav Bedia , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add minimal APIs for writing to the IPC and the M3_TXEV registers in the Control module. These will be used in a subsequent patch which adds suspend-resume support for AM33XX. Signed-off-by: Vaibhav Bedia Acked-by: Santosh Shilimkar --- Change from RFC version: No change arch/arm/mach-omap2/control.c | 20 ++++++++++++++++++++ arch/arm/mach-omap2/control.h | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 2adb268..c5d54ae 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -604,3 +604,23 @@ int omap3_ctrl_save_padconf(void) } #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ + +#if defined(CONFIG_SOC_AM33XX) && defined(CONFIG_PM) +void am33xx_txev_eoi(void) +{ + omap_ctrl_writel(AM33XX_M3_TXEV_ACK, AM33XX_CONTROL_M3_TXEV_EOI); +} + +void am33xx_txev_enable(void) +{ + omap_ctrl_writel(AM33XX_M3_TXEV_ENABLE, AM33XX_CONTROL_M3_TXEV_EOI); +} + +void am33xx_wkup_m3_ipc_cmd(struct am33xx_ipc_data *data) +{ + omap_ctrl_writel(data->resume_addr, AM33XX_CONTROL_IPC_MSG_REG0); + omap_ctrl_writel(data->sleep_mode, AM33XX_CONTROL_IPC_MSG_REG1); + omap_ctrl_writel(data->param1, AM33XX_CONTROL_IPC_MSG_REG2); + omap_ctrl_writel(data->param2, AM33XX_CONTROL_IPC_MSG_REG3); +} +#endif /* CONFIG_SOC_AM33XX && CONFIG_PM */ diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index e6c3281..cb85f0a 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -358,6 +358,37 @@ #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) +#define AM33XX_DDR_IO_CTRL 0x0E04 +#define AM33XX_VTP0_CTRL_REG 0x0E0C + +/* AM33XX VTP0_CTRL_REG bits */ +#define AM33XX_VTP_CTRL_START_EN (1 << 0) +#define AM33XX_VTP_CTRL_LOCK_EN (1 << 4) +#define AM33XX_VTP_CTRL_READY (1 << 5) +#define AM33XX_VTP_CTRL_ENABLE (1 << 6) + +/* AM33XX M3_TXEV_EOI register */ +#define AM33XX_CONTROL_M3_TXEV_EOI 0x1324 + +#define AM33XX_M3_TXEV_ACK (0x1 << 0) +#define AM33XX_M3_TXEV_ENABLE (0x0 << 0) + +/* AM33XX IPC message registers */ +#define AM33XX_CONTROL_IPC_MSG_REG0 0x1328 +#define AM33XX_CONTROL_IPC_MSG_REG1 0x132C +#define AM33XX_CONTROL_IPC_MSG_REG2 0x1330 +#define AM33XX_CONTROL_IPC_MSG_REG3 0x1334 +#define AM33XX_CONTROL_IPC_MSG_REG4 0x1338 +#define AM33XX_CONTROL_IPC_MSG_REG5 0x133C +#define AM33XX_CONTROL_IPC_MSG_REG6 0x1340 +#define AM33XX_CONTROL_IPC_MSG_REG7 0x1344 + +#define AM33XX_DDR_CMD0_IOCTRL 0x1404 +#define AM33XX_DDR_CMD1_IOCTRL 0x1408 +#define AM33XX_DDR_CMD2_IOCTRL 0x140C +#define AM33XX_DDR_DATA0_IOCTRL 0x1440 +#define AM33XX_DDR_DATA1_IOCTRL 0x1444 + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c @@ -417,6 +448,16 @@ extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); +struct am33xx_ipc_data { + u32 resume_addr; + u32 param1; + u32 param2; + u32 sleep_mode; +}; +extern void am33xx_wkup_m3_ipc_cmd(struct am33xx_ipc_data *data); +extern void am33xx_txev_eoi(void); +extern void am33xx_txev_enable(void); + #else #define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0