From patchwork Fri Jan 18 07:31:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1999751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 8BC573FD86 for ; Fri, 18 Jan 2013 07:36:57 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tw6TI-0007C2-I8; Fri, 18 Jan 2013 07:34:40 +0000 Received: from mail-da0-f46.google.com ([209.85.210.46]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tw6Qe-0005db-Qc for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2013 07:31:57 +0000 Received: by mail-da0-f46.google.com with SMTP id p5so1494306dak.19 for ; Thu, 17 Jan 2013 23:31:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=mWFh3OLciMRlDGVMLBRm7PtYGK5uy2/6VcTlCq1ANl8=; b=SsSzJns5ZY0mw1NIM0DxBfWNimB5qevIhirXTpgnP43/9Gt/rZwU8jY1Y04j0C+2A7 8mgX9GkTRyWyQbXIApWLThSjNW3BHWd1MXEHqhOfI7JSlSSVvNaIujqehCCPJeiDjVse JRsyqa0fSyuUx4sJ+XnBCMbvTyQ6dtkVqY5x4Y36/akSz1lzNH9zwNeMmLLEAuH6Y6J7 /Mp6KpYEzNsdp9PYhFNj2lijm1InUtHNouWVjDYjwUrt+yufH92AzqBTi02M48TWum9L WmuUv+AJJXj34LRIdVckkUmwqH/5AN/kS25VywCbvvwWcUpV+IQqBXZZiCpTZYFVIkLX ibjg== X-Received: by 10.68.234.229 with SMTP id uh5mr2469897pbc.123.1358494315292; Thu, 17 Jan 2013 23:31:55 -0800 (PST) Received: from localhost.localdomain ([98.126.173.75]) by mx.google.com with ESMTPS id i6sm2922899paw.19.2013.01.17.23.31.52 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 17 Jan 2013 23:31:54 -0800 (PST) From: Haojian Zhuang To: linus.walleij@linaro.org, linux@arm.linux.org.uk, tony@atomide.com, linux-arm-kernel@lists.infradead.org, swarren@nvidia.com Subject: [PATCH v7 08/15] gpio: pl061: bind pinctrl by gpio request Date: Fri, 18 Jan 2013 15:31:12 +0800 Message-Id: <1358494279-16503-9-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358494279-16503-1-git-send-email-haojian.zhuang@linaro.org> References: <1358494279-16503-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQl/QSHCezreMh03QLmDgJ0psut5DJerA4+qK6sDHei0n8drTSCbeUQHnUqFUq2tLO9/8aoY X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130118_023156_962815_EDDD4777 X-CRM114-Status: GOOD ( 13.65 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.46 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the pl061_gpio_request() to request pinctrl. Create the logic between pl061 gpio driver and pinctrl (pinctrl-single) driver. While a gpio pin is requested, it will request pinctrl driver to set that pin with gpio function mode. So pinctrl driver should append .gpio_request_enable() in pinmux_ops. Signed-off-by: Haojian Zhuang --- drivers/gpio/gpio-pl061.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 8336719..8cfdf60 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -61,6 +62,23 @@ struct pl061_gpio { #endif }; +static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + /* + * Map back to global GPIO space and request muxing, the direction + * parameter does not matter for this controller. + */ + int gpio = chip->base + offset; + + /* + * Do NOT check the return value at here. Since sometimes the gpio + * pin needn't to be configured in pinmux controller. So it's + * impossible to find the matched gpio range. + */ + pinctrl_request_gpio(gpio); + return 0; +} + static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) { struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); @@ -251,6 +269,7 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&chip->lock); + chip->gc.request = pl061_gpio_request; chip->gc.direction_input = pl061_direction_input; chip->gc.direction_output = pl061_direction_output; chip->gc.get = pl061_get_value;