From patchwork Fri Jan 18 15:27:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 2003471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id CF038DF280 for ; Fri, 18 Jan 2013 15:31:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TwDs1-0000z7-5V; Fri, 18 Jan 2013 15:28:41 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TwDqS-0000bi-2S for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2013 15:27:40 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0IFQuqp012308; Fri, 18 Jan 2013 09:26:57 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0IFQuqf019672; Fri, 18 Jan 2013 20:56:56 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Fri, 18 Jan 2013 20:56:56 +0530 Received: from ula0393909.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0IFQhPS001185; Fri, 18 Jan 2013 20:56:55 +0530 From: Santosh Shilimkar To: Subject: [PATCH 06/10] ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header Date: Fri, 18 Jan 2013 20:57:32 +0530 Message-ID: <1358522856-12180-7-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358522856-12180-1-git-send-email-santosh.shilimkar@ti.com> References: <1358522856-12180-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130118_102704_666496_7E71AD4F X-CRM114-Status: GOOD ( 18.05 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Paul Walmsley , mturquette@linaro.org, b-cousson@ti.com, tony@atomide.com, rnayak@ti.com, Santosh Shilimkar , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Benoit Cousson Add the data file to describe all power domains inside the OMAP54XX soc. Cc: Paul Walmsley Signed-off-by: Benoit Cousson [santosh.shilimkar@ti.com: Generated es2.0 data] Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/powerdomain.h | 1 + arch/arm/mach-omap2/powerdomains54xx_data.c | 331 +++++++++++++++++++++++++++ 2 files changed, 332 insertions(+) create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 5277d56eb..a2e44d2 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -239,6 +239,7 @@ extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); +extern void omap54xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c new file mode 100644 index 0000000..81f8a7c --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -0,0 +1,331 @@ +/* + * OMAP54XX Power domains framework + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include "powerdomain.h" + +#include "prcm-common.h" +#include "prcm44xx.h" +#include "prm-regbits-54xx.h" +#include "prm54xx.h" +#include "prcm_mpu54xx.h" + +/* core_54xx_pwrdm: CORE power domain */ +static struct powerdomain core_54xx_pwrdm = { + .name = "core_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CORE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* abe_54xx_pwrdm: Audio back end power domain */ +static struct powerdomain abe_54xx_pwrdm = { + .name = "abe_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_ABE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ +static struct powerdomain coreaon_54xx_pwrdm = { + .name = "coreaon_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_COREAON_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, +}; + +/* dss_54xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_54xx_pwrdm = { + .name = "dss_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_DSS_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_54xx_pwrdm = { + .name = "cpu0_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_54xx_pwrdm = { + .name = "cpu1_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu1_l1 */ + }, +}; + +/* emu_54xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_54xx_pwrdm = { + .name = "emu_pwrdm", + .voltdm = { .name = "wkup" }, + .prcm_offs = OMAP54XX_PRM_EMU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, +}; + +/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_54xx_pwrdm = { + .name = "mpu_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRM_MPU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_OFF_RET, /* mpu_ram */ + }, +}; + +/* custefuse_54xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain custefuse_54xx_pwrdm = { + .name = "custefuse_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* dsp_54xx_pwrdm: Tesla processor power domain */ +static struct powerdomain dsp_54xx_pwrdm = { + .name = "dsp_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_DSP_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dsp_edma */ + [1] = PWRSTS_OFF_RET, /* dsp_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dsp_edma */ + [1] = PWRSTS_OFF_RET, /* dsp_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp_l2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cam_54xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_54xx_pwrdm = { + .name = "cam_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CAM_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cam_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* cam_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_54xx_pwrdm = { + .name = "l3init_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_L3INIT_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* gpu_54xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gpu_54xx_pwrdm = { + .name = "gpu_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_GPU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* wkupaon_54xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkupaon_54xx_pwrdm = { + .name = "wkupaon_pwrdm", + .voltdm = { .name = "wkup" }, + .prcm_offs = OMAP54XX_PRM_WKUPAON_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, + .banks = 1, + .pwrsts_mem_ret = { + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* wkup_bank */ + }, +}; + +/* iva_54xx_pwrdm: IVA-HD power domain */ +static struct powerdomain iva_54xx_pwrdm = { + .name = "iva_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_IVA_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* + * The following power domains are not under SW control + * + * mpuaon + * mmaon + */ + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap54xx[] __initdata = { + &core_54xx_pwrdm, + &abe_54xx_pwrdm, + &coreaon_54xx_pwrdm, + &dss_54xx_pwrdm, + &cpu0_54xx_pwrdm, + &cpu1_54xx_pwrdm, + &emu_54xx_pwrdm, + &mpu_54xx_pwrdm, + &custefuse_54xx_pwrdm, + &dsp_54xx_pwrdm, + &cam_54xx_pwrdm, + &l3init_54xx_pwrdm, + &gpu_54xx_pwrdm, + &wkupaon_54xx_pwrdm, + &iva_54xx_pwrdm, + NULL +}; + +void __init omap54xx_powerdomains_init(void) +{ + pwrdm_register_platform_funcs(&omap4_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap54xx); + pwrdm_complete_init(); +}