From patchwork Fri Jan 18 15:32:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 2003581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 2334A3FD86 for ; Fri, 18 Jan 2013 15:35:26 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TwDwO-0004H7-CJ; Fri, 18 Jan 2013 15:33:12 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TwDup-0003E4-95 for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2013 15:31:37 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0IFVVtI012877; Fri, 18 Jan 2013 09:31:32 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0IFVVxM020537; Fri, 18 Jan 2013 21:01:31 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Fri, 18 Jan 2013 21:01:31 +0530 Received: from ula0393909.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0IFVRvm001586; Fri, 18 Jan 2013 21:01:31 +0530 From: Santosh Shilimkar To: Subject: [PATCH 5/5] ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer Date: Fri, 18 Jan 2013 21:02:21 +0530 Message-ID: <1358523141-12295-6-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358523141-12295-1-git-send-email-santosh.shilimkar@ti.com> References: <1358523141-12295-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130118_103135_462879_DD47CB33 X-CRM114-Status: UNSURE ( 8.84 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: tony@atomide.com, Rajendra Nayak , Santosh Shilimkar , Benoit Cousson , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Rajendra Nayak Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot.. [ 0.000000] arch_timer: No interrupt available, giving up Cc: Benoit Cousson Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 790bb2a..7a78d1b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -35,8 +35,12 @@ compatible = "arm,cortex-a15"; timer { compatible = "arm,armv7-timer"; - /* 14th PPI IRQ, active low level-sensitive */ - interrupts = <1 14 0x308>; + /* + * PPI secure/nonsecure IRQ, + * active low level-sensitive + */ + interrupts = <1 13 0x308>, + <1 14 0x308>; clock-frequency = <6144000>; }; }; @@ -44,8 +48,12 @@ compatible = "arm,cortex-a15"; timer { compatible = "arm,armv7-timer"; - /* 14th PPI IRQ, active low level-sensitive */ - interrupts = <1 14 0x308>; + /* + * PPI secure/nonsecure IRQ, + * active low level-sensitive + */ + interrupts = <1 13 0x308>, + <1 14 0x308>; clock-frequency = <6144000>; }; };