From patchwork Wed Jan 23 16:57:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 2026151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 7F2A13FE4F for ; Wed, 23 Jan 2013 16:59:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Ty3dS-0001Th-SB; Wed, 23 Jan 2013 16:57:14 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Ty3dQ-0001TI-IA for linux-arm-kernel@lists.infradead.org; Wed, 23 Jan 2013 16:57:13 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 4C31D635D; Wed, 23 Jan 2013 09:59:10 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 9B690E40EB; Wed, 23 Jan 2013 09:57:10 -0700 (MST) From: Stephen Warren To: Stephen Warren Subject: [PATCH] ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi Date: Wed, 23 Jan 2013 09:57:02 -0700 Message-Id: <1358960222-22705-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130123_115712_668472_A89F3547 X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, Stephen Warren , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-beaver.dts | 1 - arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 -- arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 0f296a4..8ff2ff2 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -90,7 +90,6 @@ serial@70006000 { status = "okay"; - clock-frequency = <408000000>; }; i2c@7000c000 { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index ff6b68f..1749927 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -120,13 +120,11 @@ serial@70006000 { status = "okay"; - clock-frequency = <408000000>; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; status = "okay"; - clock-frequency = <408000000>; }; i2c@7000c000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ff4a0ca..313fa71 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -234,6 +234,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + clock-frequency = <408000000>; nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car 6>; status = "disabled"; @@ -243,6 +244,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car 160>; @@ -253,6 +255,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 46 0x04>; nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car 55>; @@ -263,6 +266,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 90 0x04>; nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car 65>; @@ -273,6 +277,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 91 0x04>; nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car 66>;