| Message ID | 1359388467-32386-3-git-send-email-pdeschrijver@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 01/28/2013 08:54 AM, Peter De Schrijver wrote: > The tegra peripheral clock type uses struct clk_mux directly, so it needs to > be updated to handle the new mask and table fields. Also the macros need > to be updated Just a quick note on patch dependencies here: Patch 1/2 can presumably be taken through the clk tree whenever Mike is OK with it. Patch 2/2 depends on patches in the Tegra tree for 3.9. Since patch 2/2 is useful mostly for the Tegra114 clock driver, and I don't imagine that will get posted/merged in time for 3.9, it's probably easiest to just take patch 2/2 for 3.10 along with the Tegra114 clock driver. Also, I imagine there won't be any more clk/Tegra tree dependencies in 3.10, so patch 2/2 and the Tegra114 clk driver patches can likely go through the clk tree itself for 3.10.
On Mon, Jan 28, 2013 at 05:49:53PM +0100, Stephen Warren wrote: > On 01/28/2013 08:54 AM, Peter De Schrijver wrote: > > The tegra peripheral clock type uses struct clk_mux directly, so it needs to > > be updated to handle the new mask and table fields. Also the macros need > > to be updated > > Just a quick note on patch dependencies here: > > Patch 1/2 can presumably be taken through the clk tree whenever Mike is > OK with it. > > Patch 2/2 depends on patches in the Tegra tree for 3.9. Since patch 2/2 > is useful mostly for the Tegra114 clock driver, and I don't imagine that > will get posted/merged in time for 3.9, it's probably easiest to just > take patch 2/2 for 3.10 along with the Tegra114 clock driver. Also, I > imagine there won't be any more clk/Tegra tree dependencies in 3.10, so > patch 2/2 and the Tegra114 clk driver patches can likely go through the > clk tree itself for 3.10. No. Because 1/2 changes struct clk_mux and the tegra peripheral clock type uses struct clk_mux directly, 2/2 needs to be applied together with 1/2, even if the new functionality is not yet used. Cheers, Peter.
On 01/29/2013 02:51 AM, Peter De Schrijver wrote: > On Mon, Jan 28, 2013 at 05:49:53PM +0100, Stephen Warren wrote: >> On 01/28/2013 08:54 AM, Peter De Schrijver wrote: >>> The tegra peripheral clock type uses struct clk_mux directly, so it needs to >>> be updated to handle the new mask and table fields. Also the macros need >>> to be updated >> >> Just a quick note on patch dependencies here: >> >> Patch 1/2 can presumably be taken through the clk tree whenever Mike is >> OK with it. >> >> Patch 2/2 depends on patches in the Tegra tree for 3.9. Since patch 2/2 >> is useful mostly for the Tegra114 clock driver, and I don't imagine that >> will get posted/merged in time for 3.9, it's probably easiest to just >> take patch 2/2 for 3.10 along with the Tegra114 clock driver. Also, I >> imagine there won't be any more clk/Tegra tree dependencies in 3.10, so >> patch 2/2 and the Tegra114 clk driver patches can likely go through the >> clk tree itself for 3.10. > > No. Because 1/2 changes struct clk_mux and the tegra peripheral clock type > uses struct clk_mux directly, 2/2 needs to be applied together with 1/2, even > if the new functionality is not yet used. Oh, then they can't be two separate patches then, or "git bisect" won't work. I guess it's best to wait for 3.10 for this:-(
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 0744731..a09d7dc 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -355,15 +355,16 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name, struct tegra_clk_periph *periph, void __iomem *clk_base, u32 offset); -#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \ +#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ _div_shift, _div_width, _div_frac_width, \ _div_flags, _clk_num, _enb_refcnt, _regs, \ - _gate_flags) \ + _gate_flags, _table) \ { \ .mux = { \ .flags = _mux_flags, \ .shift = _mux_shift, \ - .width = _mux_width, \ + .mask = _mux_mask, \ + .table = _table, \ }, \ .divider = { \ .flags = _div_flags, \ @@ -393,26 +394,36 @@ struct tegra_periph_init_data { const char *dev_id; }; -#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \ - _mux_shift, _mux_width, _mux_flags, _div_shift, \ +#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ + _mux_shift, _mux_mask, _mux_flags, _div_shift, \ _div_width, _div_frac_width, _div_flags, _regs, \ - _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ + _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \ { \ .name = _name, \ .clk_id = _clk_id, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ - .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \ + .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ _mux_flags, _div_shift, \ _div_width, _div_frac_width, \ _div_flags, _clk_num, \ _enb_refcnt, _regs, \ - _gate_flags), \ + _gate_flags, _table), \ .offset = _offset, \ .con_id = _con_id, \ .dev_id = _dev_id, \ } +#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ + _mux_shift, _mux_width, _mux_flags, _div_shift, \ + _div_width, _div_frac_width, _div_flags, _regs, \ + _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ + TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ + _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ + _div_shift, _div_width, _div_frac_width, _div_flags, \ + _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ + NULL) + /** * struct clk_super_mux - super clock *
The tegra peripheral clock type uses struct clk_mux directly, so it needs to be updated to handle the new mask and table fields. Also the macros need to be updated Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- drivers/clk/tegra/clk.h | 27 +++++++++++++++++++-------- 1 files changed, 19 insertions(+), 8 deletions(-)