From patchwork Fri Feb 1 06:20:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 2076731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 4D0C3DFE75 for ; Fri, 1 Feb 2013 06:14:32 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U19rG-00078G-0r; Fri, 01 Feb 2013 06:12:18 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U19r4-00075o-Bi for linux-arm-kernel@lists.infradead.org; Fri, 01 Feb 2013 06:12:08 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MHJ00CBW2JA9UO0@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 01 Feb 2013 15:12:01 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id FC.E1.03918.1BC5B015; Fri, 01 Feb 2013 15:12:01 +0900 (KST) X-AuditID: cbfee61a-b7f7d6d000000f4e-c6-510b5cb16c9f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id BC.E1.03918.1BC5B015; Fri, 01 Feb 2013 15:12:01 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MHJ003512JP2WB0@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 01 Feb 2013 15:12:01 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com Subject: [PATCH] ARM: EXYNOS5: Fix PMU register configuration for local power blocks Date: Fri, 01 Feb 2013 11:50:26 +0530 Message-id: <1359699626-28525-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkRndjDHegwd9mGYtNj6+xOjB6bF5S H8AYxWWTkpqTWZZapG+XwJWxfHInU8FctYrm97MYGxiXKXQxcnJICJhIXP6zhBXCFpO4cG89 WxcjF4eQwFJGifnb7jLCFB2ZdZ0FIrGIUaK7/TorhLOdSeLVnU9MIFVsAnoSC/59ZQaxRQRS JH487QOLMwu4S8ze9wrI5uAQFgiT+LKkEiTMIqAqMf3garAFvAKuEn0fvzODlEgIKEjMmWQD Ml5CYAebRMflXawQ9QIS3yYfYoGokZXYdIAZ4jZJiYMrbrBMYBRcwMiwilE0tSC5oDgpPddQ rzgxt7g0L10vOT93EyMwoE7/eya1g3Flg8UhRgEORiUe3oLvXIFCrIllxZW5hxglOJiVRHiX OHIHCvGmJFZWpRblxxeV5qQWH2JMBlo+kVlKNDkfGOx5JfGGxibmpsamlkZGZqampAkrifMy nnoSICSQnliSmp2aWpBaBLOFiYNTqoFx87KINd9nveDYcvqO6nET4eXbknuLNULDbjcZ7fK4 +XdBpsC91vlaC5wEnD2WB7xziNm/a/2cLIbWLfFfckUn5Qrc11ps/8dBbHL13NInr1bVHSp/ dYv/yKw5nZ31KU26D5wXnffiinnfY/iwR770UzfzJ9bdp5lyvSt1jG5Oetjz5tWFlxXCSizF GYmGWsxFxYkASX/TGmwCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e+xgO7GGO5Ag19zeS02Pb7G6sDosXlJ fQBjVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Q VCWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYQ1jxvLJnUwFc9Uqmt/PYmxg XKbQxcjJISFgInFk1nUWCFtM4sK99WxdjFwcQgKLGCW626+zQjjbmSRe3fnEBFLFJqAnseDf V2YQW0QgReLH0z6wOLOAu8Tsfa+AbA4OYYEwiS9LKkHCLAKqEtMPrmYEsXkFXCX6Pn5nBimR EFCQmDPJZgIj9wJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5uZsYweH6TGoH48oGi0OMAhyM Sjy8Bd+5AoVYE8uKK3MPMUpwMCuJ8C5x5A4U4k1JrKxKLcqPLyrNSS0+xJgMtHwis5Rocj4w lvJK4g2NTcxNjU0tTSxMzCxJE1YS52U89SRASCA9sSQ1OzW1ILUIZgsTB6dUA2ODwcHo3FeN 1tu2fpdj+baRKSKFj+/UXZ7DM978E+i8m3RQebLvjkX266omNc1sL3NYpH40ouKKg9HbA8UH 9hcJeIaLTlG2t1++xjFHdJmA0XTOUJ/fnwqtOhZOvfBgXSur8YZUkZltXLku1dz3dSeYFf9X +tyTybVE2nWi8L8IyVVxjBYafkosxRmJhlrMRcWJALpHC06bAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130201_011206_859283_52781D11 X-CRM114-Status: GOOD ( 11.28 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 UPPERCASE_50_75 message body is 50-75% uppercase Cc: Abhilash Kesavan , kyungmin.park@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need to be low initially for normal mode on Exynos5250. Also fix the corresponding AFTR and LPA configurations. Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/pmu.c | 66 ++++++++++++++++++++++++++++++++------------ 1 file changed, 48 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index daebc1a..61cedd7 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -295,24 +295,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, { PMU_TABLE_END,}, }; @@ -336,6 +336,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ISP_ARM_OPTION, }; +void __iomem *exynos5_list_disable_pmu_reg[] = { + EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, + EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, + EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, + EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, + EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, + EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, +}; + static void exynos5_init_pmu(void) { unsigned int i; @@ -392,6 +413,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) static int __init exynos_pmu_init(void) { unsigned int value; + unsigned int i; exynos_pmu_config = exynos4210_pmu_config; @@ -414,6 +436,14 @@ static int __init exynos_pmu_init(void) value &= ~EXYNOS5_SYS_WDTRESET; __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); + /* + * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers for + * local power blocks to Low initially as per the "System-Level + * Power-Down Configuration Registers" table. + */ + for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++) + __raw_writel(0x0, exynos5_list_disable_pmu_reg[i]); + exynos_pmu_config = exynos5250_pmu_config; pr_info("EXYNOS5250 PMU Initialize\n"); } else {