From patchwork Fri Feb 1 16:38:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 2081221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 4874840106 for ; Fri, 1 Feb 2013 16:41:34 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U1Jdm-0002uJ-KU; Fri, 01 Feb 2013 16:39:02 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U1Jdd-0002rU-Vj for linux-arm-kernel@lists.infradead.org; Fri, 01 Feb 2013 16:38:54 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r11Gcpjc024433; Fri, 1 Feb 2013 10:38:51 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r11Gcp3B025085; Fri, 1 Feb 2013 10:38:51 -0600 Received: from dlelxv24.itg.ti.com (172.17.1.199) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Fri, 1 Feb 2013 10:38:50 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r11Gcomi028730; Fri, 1 Feb 2013 10:38:50 -0600 Received: from localhost (h16-8.vpn.ti.com [172.24.16.8]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r11GcoV16524; Fri, 1 Feb 2013 10:38:50 -0600 (CST) From: Jon Hunter To: Tony Lindgren Subject: [PATCH 2/2] ARM: OMAP2: Fix GPMC memory initialisation Date: Fri, 1 Feb 2013 10:38:46 -0600 Message-ID: <1359736726-10193-3-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1359736726-10193-1-git-send-email-jon-hunter@ti.com> References: <1359736726-10193-1-git-send-email-jon-hunter@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130201_113854_106519_B94C6AB7 X-CRM114-Status: GOOD ( 21.08 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.41 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Afzal Mohammed , linux-omap , Jon Hunter , linux-arm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org OMAP2+ devices have an internal ROM that by default is typically mapped to the first 1MB of the GPMC address space (0x0). For OMAP24xx devices, GPMC chip-select 0 (CS0) may be mapped to address 0x0 instead of the internal ROM if configured for an external boot mode. If configured for an internal boot mode then the internal ROM is mapped to 0x0. Currently, the function gpmc_mem_init() function reserves the first 1MB of GPMC address space for the internal OMAP ROM with the exception of the OMAP2 APOLLON board. This prevents any device (ethernet chip, flash memories, etc) from using this address range. This causes the GPMC probe to fail on the OMAP2420 H4 when NOR flash is mapped to address 0x0. Fix this by testing the boot mode for OMAP24xx devices to see if the SYS_BOOT3 is low, indicating an external boot, and thus GPMC CS0 is mapped to 0x0. Please note that for OMAP3-5 devices, when booting from NOR or NAND memories connected to CS0, these memories are always mapped to address 0x08000000 and so reserving this memory range does not present any problems for these devices. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/gpmc.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 441cc63..9486b8e 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -32,6 +32,7 @@ #include "soc.h" #include "common.h" +#include "control.h" #include "omap_device.h" #include "gpmc.h" @@ -778,18 +779,26 @@ static void gpmc_mem_exit(void) static int gpmc_mem_init(void) { int cs, rc; - unsigned long boot_rom_space = 0; - /* never allocate the first page, to facilitate bug detection; - * even if we didn't boot from ROM. + /* + * The first 1MB of GPMC address space is mapped to the + * internal ROM. OMAP2 devices are an exception to this + * where the first 1MB may be mapped to the GPMC. */ - boot_rom_space = BOOT_ROM_SPACE; - /* In apollon the CS0 is mapped as 0x0000 0000 */ - if (machine_is_omap_apollon()) - boot_rom_space = 0; - gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; + gpmc_mem_root.start = GPMC_MEM_START + BOOT_ROM_SPACE; gpmc_mem_root.end = GPMC_MEM_END; + /* + * OMAP2 devices that boot from external memory devices, will + * map CS0 to the start of the GPMC address space (0x0). We can + * test this by checking if SYS_BOOT3 pin is set. If not set + * then CS0 is mapped to 0x0. + */ + if (cpu_is_omap24xx()) + if (!(omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) & + OMAP2_SYSBOOT_3_MASK)) + gpmc_mem_root.start = GPMC_MEM_START; + /* Reserve all regions that has been set up by bootloader */ for (cs = 0; cs < GPMC_CS_NUM; cs++) { u32 base, size;