From patchwork Wed Feb 13 19:14:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sherman Yin X-Patchwork-Id: 2139041 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 52536DFE75 for ; Wed, 13 Feb 2013 19:13:42 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U5hj5-0007NQ-RO; Wed, 13 Feb 2013 19:10:39 +0000 Received: from mms2.broadcom.com ([216.31.210.18]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U5hj3-0007N8-IZ for linux-arm-kernel@lists.infradead.org; Wed, 13 Feb 2013 19:10:38 +0000 Received: from [10.9.208.55] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Wed, 13 Feb 2013 11:07:05 -0800 X-Server-Uuid: 4500596E-606A-40F9-852D-14843D8201B2 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS07.corp.ad.broadcom.com (10.9.208.55) with Microsoft SMTP Server (TLS) id 14.1.438.0; Wed, 13 Feb 2013 11:10:25 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.1.438.0; Wed, 13 Feb 2013 11:10:25 -0800 Received: from ltrmn-lnxub75-vm (testboard-syin2.ric.broadcom.com [10.136.4.120]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 8F9FB40FE6; Wed, 13 Feb 2013 11:10:25 -0800 (PST) Received: by ltrmn-lnxub75-vm (Postfix, from userid 35077) id 097DB61CD8; Wed, 13 Feb 2013 11:15:08 -0800 (PST) From: "Sherman Yin" To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: Fix up l2x0_init log message Date: Wed, 13 Feb 2013 11:14:53 -0800 Message-ID: <1360782893-20969-2-git-send-email-syin@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360782893-20969-1-git-send-email-syin@broadcom.com> References: <1360782893-20969-1-git-send-email-syin@broadcom.com> MIME-Version: 1.0 X-WSS-ID: 7D053BD33QG2842811-01-01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130213_141037_775085_610D1B43 X-CRM114-Status: GOOD ( 12.95 ) X-Spam-Score: -4.9 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [216.31.210.18 listed in list.dnswl.org] -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: csd@broadcom.com, Sherman Yin , mmayer@broadcom.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The log at the end of l2x0_init() should print L2 cache info based on current register value instead of function argument. --- arch/arm/mm/cache-l2x0.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c2f3739..011a584 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -377,14 +377,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) l2x0_way_mask = (1 << ways) - 1; /* - * L2 cache Size = Way size * Number of ways - */ - way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; - way_size = 1 << (way_size + way_size_shift); - - l2x0_size = ways * way_size * SZ_1K; - - /* * Check if l2x0 controller is already enabled. * If you are booting from non-secure mode * accessing the below registers will fault. @@ -418,6 +410,37 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.disable = l2x0_disable; } + /* Update number of ways based on aux ctrl register value */ + switch (cache_id) { + case L2X0_CACHE_ID_PART_L310: + if (aux & (1 << 16)) + ways = 16; + else + ways = 8; + break; + case L2X0_CACHE_ID_PART_L210: + ways = (aux >> 13) & 0xf; + break; + + case AURORA_CACHE_ID: + ways = (aux >> 13) & 0xf; + ways = 2 << ((ways + 1) >> 2); + way_size_shift = AURORA_WAY_SIZE_SHIFT; + break; + default: + /* Assume unknown chips have 8 ways */ + ways = 8; + break; + } + + /* + * L2 cache Size = Way size * Number of ways + */ + way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; + way_size = 1 << (way_size + way_size_shift); + + l2x0_size = ways * way_size * SZ_1K; + printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", ways, cache_id, aux, l2x0_size);