From patchwork Mon Feb 18 05:12:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2155561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id C8D93DF25A for ; Mon, 18 Feb 2013 05:19:01 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U7J5g-0002Y9-BD; Mon, 18 Feb 2013 05:16:36 +0000 Received: from mail-pb0-f49.google.com ([209.85.160.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U7J3f-0000yr-Mp for linux-arm-kernel@lists.infradead.org; Mon, 18 Feb 2013 05:14:33 +0000 Received: by mail-pb0-f49.google.com with SMTP id xa12so1484972pbc.36 for ; Sun, 17 Feb 2013 21:14:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=3c7K2G4i2FRVd1xUq80EEtKmqAh2NnRN9Bo7mQhFraY=; b=K+lJHMflnPPJPWNlGv3vtRB5DFpnpHaPaMlHqvG7GvPi2rx5qMvCI5cUdbL3mr8s4+ ALrezccum8Vlse4UcpOeEKMVLTY9q6xW5FHXS7+y2R21Sf1hbXokGDRhszViJwmohSJJ uJQw0q0vpRqChsG+/OGX6C/PFoh0KAn4xsVdcUXVT1VE/FiFWXt59T942107eUFTC4f3 gr7+fz+bbkG3y95Hi2cxK5rD/fuoG8BzzymnKkgSPYW5zPXjAp0z9UTc4xQSYYp3KBUr H8mxy95COPqitzzrEugqn8gjxUNQX/HlXScvnF7njmoCU9NhKbtG9sgyp6h+cRFic+MT /bZw== X-Received: by 10.66.74.234 with SMTP id x10mr32965650pav.10.1361164467573; Sun, 17 Feb 2013 21:14:27 -0800 (PST) Received: from localhost.localdomain ([140.206.155.71]) by mx.google.com with ESMTPS id ni3sm13194880pbc.31.2013.02.17.21.14.19 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Feb 2013 21:14:26 -0800 (PST) From: Haojian Zhuang To: grinberg@compulab.co.il, linus.walleij@linaro.org, linux@arm.linux.org.uk, marek.vasut@gmail.com, robert.jarzmik@free.fr, daniel@caiaq.de, linux-arm-kernel@lists.infradead.org, grant.likely@secretlab.ca, cxie4@marvell.com Subject: [PATCH v3 11/12] gpio: pxa: discard irq base in pxa_gpio_chip Date: Mon, 18 Feb 2013 13:12:37 +0800 Message-Id: <1361164358-5845-12-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1361164358-5845-1-git-send-email-haojian.zhuang@linaro.org> References: <1361164358-5845-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQm7TOchFpiZsdQO4eTfsfLIh4dWnRREeJC2qUTkWqafyQVTpq7uLlct8Px54RzAtdT3+tNZ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130218_001431_939844_15ACEC47 X-CRM114-Status: GOOD ( 18.71 ) X-Spam-Score: 0.4 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Discard irq_base in struct pxa_gpio_chip. Use irq_domain instead. Signed-off-by: Haojian Zhuang Acked-by: Linus Walleij --- drivers/gpio/gpio-pxa.c | 91 +++++++++++++++++++++++------------------------ 1 file changed, 44 insertions(+), 47 deletions(-) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 35cdb23..d45cb57 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -66,8 +66,8 @@ int pxa_last_gpio; struct pxa_gpio_chip { struct gpio_chip chip; + struct irq_domain *domain; void __iomem *regbase; - unsigned int irq_base; bool inverted; bool gafr; char label[10]; @@ -147,17 +147,7 @@ static int pxa_gpio_to_irq(struct gpio_chip *gc, unsigned offset) struct pxa_gpio_chip *chip = NULL; chip = container_of(gc, struct pxa_gpio_chip, chip); - return chip->irq_base + offset; -} - -int pxa_irq_to_gpio(struct irq_data *d) -{ - struct pxa_gpio_chip *chip; - int gpio; - - chip = (struct pxa_gpio_chip *)d->domain->host_data; - gpio = d->irq - chip->irq_base + chip->chip.base; - return gpio; + return irq_create_mapping(chip->domain, offset); } static int pxa_gpio_request(struct gpio_chip *gc, unsigned offset) @@ -270,18 +260,19 @@ static inline void update_edge_detect(struct pxa_gpio_chip *chip) static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) { - struct pxa_gpio_chip *chip; - int gpio = pxa_irq_to_gpio(d); - unsigned long gpdr, mask = GPIO_bit(gpio); + struct pxa_gpio_chip *chip = irq_data_get_irq_chip_data(d); + int offset = irqd_to_hwirq(d); + int gpio; + unsigned long gpdr, mask; - chip = gpio_to_pxachip(gpio); + mask = 1 << offset; + gpio = chip->chip.base + offset; if (type == IRQ_TYPE_PROBE) { /* Don't mess with enabled GPIOs using preconfigured edges or * GPIOs set to alternate function or to output during probe */ - if ((chip->irq_edge_rise | chip->irq_edge_fall) - & GPIO_bit(gpio)) + if ((chip->irq_edge_rise | chip->irq_edge_fall) & mask) return 0; if (__gpio_is_occupied(chip, gpio)) @@ -318,16 +309,15 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) { struct pxa_gpio_chip *chip; - int loop, gpio, gpio_base, n; - unsigned long gedr; struct irq_chip *ic = irq_desc_get_chip(desc); + int n, gpio, loop; + unsigned long gedr; chained_irq_enter(ic, desc); do { loop = 0; for_each_gpio_chip(gpio, chip) { - gpio_base = chip->chip.base; gedr = readl_relaxed(chip->regbase + GEDR_OFFSET); gedr = gedr & chip->irq_mask; @@ -335,8 +325,8 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) for_each_set_bit(n, &gedr, BITS_PER_LONG) { loop = 1; - - generic_handle_irq(gpio_to_irq(gpio_base + n)); + generic_handle_irq(pxa_gpio_to_irq(&chip->chip, + n)); } } } while (loop); @@ -346,31 +336,35 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) static void pxa_ack_muxed_gpio(struct irq_data *d) { - int gpio = pxa_irq_to_gpio(d); - struct pxa_gpio_chip *chip = gpio_to_pxachip(gpio); + struct pxa_gpio_chip *chip = irq_data_get_irq_chip_data(d); + int offset = irqd_to_hwirq(d); - writel_relaxed(GPIO_bit(gpio), chip->regbase + GEDR_OFFSET); + writel_relaxed(1 << offset, chip->regbase + GEDR_OFFSET); } static void pxa_mask_muxed_gpio(struct irq_data *d) { - int gpio = pxa_irq_to_gpio(d); - struct pxa_gpio_chip *chip = gpio_to_pxachip(gpio); + struct pxa_gpio_chip *chip = irq_data_get_irq_chip_data(d); + int offset = irqd_to_hwirq(d); + int mask; uint32_t grer, gfer; - chip->irq_mask &= ~GPIO_bit(gpio); + mask = 1 << offset; + chip->irq_mask &= ~mask; - grer = readl_relaxed(chip->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); - gfer = readl_relaxed(chip->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); + grer = readl_relaxed(chip->regbase + GRER_OFFSET) & ~mask; + gfer = readl_relaxed(chip->regbase + GFER_OFFSET) & ~mask; writel_relaxed(grer, chip->regbase + GRER_OFFSET); writel_relaxed(gfer, chip->regbase + GFER_OFFSET); } static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) { - int gpio = pxa_irq_to_gpio(d); - struct pxa_gpio_chip *chip = gpio_to_pxachip(gpio); + struct pxa_gpio_chip *chip = irq_data_get_irq_chip_data(d); + int offset = irqd_to_hwirq(d); + int gpio; + gpio = chip->chip.base + offset; if (chip->set_wake) return chip->set_wake(gpio, on); else @@ -379,10 +373,10 @@ static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) static void pxa_unmask_muxed_gpio(struct irq_data *d) { - int gpio = pxa_irq_to_gpio(d); - struct pxa_gpio_chip *chip = gpio_to_pxachip(gpio); + struct pxa_gpio_chip *chip = irq_data_get_irq_chip_data(d); + int offset = irqd_to_hwirq(d); - chip->irq_mask |= GPIO_bit(gpio); + chip->irq_mask |= 1 << offset; update_edge_detect(chip); } @@ -395,12 +389,16 @@ static struct irq_chip pxa_muxed_gpio_chip = { .irq_set_wake = pxa_gpio_set_wake, }; -static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, +static int pxa_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw) { - irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, - handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + struct pxa_gpio_chip *chip = d->host_data; + + irq_set_chip_and_handler_name(virq, &pxa_muxed_gpio_chip, + handle_edge_irq, "gpio"); + irq_set_chip_data(virq, chip); + irq_set_irq_type(virq, IRQ_TYPE_NONE); + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); return 0; } @@ -483,13 +481,12 @@ static int pxa_init_gpio_chip(struct platform_device *pdev, int gpio_end, if (pdata->irq_base) irq_base = pdata->irq_base + gpio; else - irq_base = -1; - chips[i].irq_base = irq_alloc_descs(irq_base, 0, gc->ngpio, 0); - if (chips[i].irq_base < 0) - return -EINVAL; - if (!irq_domain_add_legacy(pdev->dev.of_node, gc->ngpio, - chips[i].irq_base, 0, - &pxa_irq_domain_ops, &chips[i])) + irq_base = 0; + chips[i].domain = irq_domain_add_simple(pdev->dev.of_node, + gc->ngpio, irq_base, + &pxa_irq_domain_ops, + &chips[i]); + if (!chips[i].domain) return -ENODEV; gc->base = gpio;