diff mbox

[1/9] ARM: OMAP4+: Use common scratchpad SAR RAM offsets for all architectures

Message ID 1361373527-21695-2-git-send-email-santosh.shilimkar@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Santosh Shilimkar Feb. 20, 2013, 3:18 p.m. UTC
From: Tero Kristo <t-kristo@ti.com>

Simplifies code and also allows the re-use as is on OMAP5 devices.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/omap4-sar-layout.h |   14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Kevin Hilman March 27, 2013, 6:41 p.m. UTC | #1
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:

> From: Tero Kristo <t-kristo@ti.com>
>
> Simplifies code and also allows the re-use as is on OMAP5 devices.

nit: changelog here is rather weak.  It claims "simplifies code" but
it's not obvious from the patch how changing a few #defines does that.

Kevin

> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-omap2/omap4-sar-layout.h |   14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
> index e170fe8..6822d0a 100644
> --- a/arch/arm/mach-omap2/omap4-sar-layout.h
> +++ b/arch/arm/mach-omap2/omap4-sar-layout.h
> @@ -20,13 +20,13 @@
>  #define SAR_BANK4_OFFSET		0x3000
>  
>  /* Scratch pad memory offsets from SAR_BANK1 */
> -#define SCU_OFFSET0				0xd00
> -#define SCU_OFFSET1				0xd04
> -#define OMAP_TYPE_OFFSET			0xd10
> -#define L2X0_SAVE_OFFSET0			0xd14
> -#define L2X0_SAVE_OFFSET1			0xd18
> -#define L2X0_AUXCTRL_OFFSET			0xd1c
> -#define L2X0_PREFETCH_CTRL_OFFSET		0xd20
> +#define SCU_OFFSET0				0xfe4
> +#define SCU_OFFSET1				0xfe8
> +#define OMAP_TYPE_OFFSET			0xfec
> +#define L2X0_SAVE_OFFSET0			0xff0
> +#define L2X0_SAVE_OFFSET1			0xff4
> +#define L2X0_AUXCTRL_OFFSET			0xff8
> +#define L2X0_PREFETCH_CTRL_OFFSET		0xffc
>  
>  /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
>  #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
Tony Lindgren March 27, 2013, 8:49 p.m. UTC | #2
* Santosh Shilimkar <santosh.shilimkar@ti.com> [130327 13:52]:
> On Thursday 28 March 2013 12:11 AM, Kevin Hilman wrote:
> > Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> > 
> >> From: Tero Kristo <t-kristo@ti.com>
> >>
> >> Simplifies code and also allows the re-use as is on OMAP5 devices.
> > 
> > nit: changelog here is rather weak.  It claims "simplifies code" but
> > it's not obvious from the patch how changing a few #defines does that.
> > 
> I agree. Basically the offset are chosen such a way that they can
> work on OMAP4 and OMAP5 instead of having two separate sets.
> Will expand the changelog to make it clear.

You might want to mention also that the offsets are only used by
the kernel to save and restore registers from so people don't
think those are hardare registers and that the patch might break
some things.

Regards,

Tony
Santosh Shilimkar March 27, 2013, 8:49 p.m. UTC | #3
On Thursday 28 March 2013 12:11 AM, Kevin Hilman wrote:
> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> 
>> From: Tero Kristo <t-kristo@ti.com>
>>
>> Simplifies code and also allows the re-use as is on OMAP5 devices.
> 
> nit: changelog here is rather weak.  It claims "simplifies code" but
> it's not obvious from the patch how changing a few #defines does that.
> 
I agree. Basically the offset are chosen such a way that they can
work on OMAP4 and OMAP5 instead of having two separate sets.
Will expand the changelog to make it clear.

Regards,
Santosh
Santosh Shilimkar March 27, 2013, 8:52 p.m. UTC | #4
On Thursday 28 March 2013 02:19 AM, Tony Lindgren wrote:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [130327 13:52]:
>> On Thursday 28 March 2013 12:11 AM, Kevin Hilman wrote:
>>> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>>>
>>>> From: Tero Kristo <t-kristo@ti.com>
>>>>
>>>> Simplifies code and also allows the re-use as is on OMAP5 devices.
>>>
>>> nit: changelog here is rather weak.  It claims "simplifies code" but
>>> it's not obvious from the patch how changing a few #defines does that.
>>>
>> I agree. Basically the offset are chosen such a way that they can
>> work on OMAP4 and OMAP5 instead of having two separate sets.
>> Will expand the changelog to make it clear.
> 
> You might want to mention also that the offsets are only used by
> the kernel to save and restore registers from so people don't
> think those are hardare registers and that the patch might break
> some things.
> 
Yeah. Will mention that.

Regards,
Santosh
diff mbox

Patch

diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index e170fe8..6822d0a 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -20,13 +20,13 @@ 
 #define SAR_BANK4_OFFSET		0x3000
 
 /* Scratch pad memory offsets from SAR_BANK1 */
-#define SCU_OFFSET0				0xd00
-#define SCU_OFFSET1				0xd04
-#define OMAP_TYPE_OFFSET			0xd10
-#define L2X0_SAVE_OFFSET0			0xd14
-#define L2X0_SAVE_OFFSET1			0xd18
-#define L2X0_AUXCTRL_OFFSET			0xd1c
-#define L2X0_PREFETCH_CTRL_OFFSET		0xd20
+#define SCU_OFFSET0				0xfe4
+#define SCU_OFFSET1				0xfe8
+#define OMAP_TYPE_OFFSET			0xfec
+#define L2X0_SAVE_OFFSET0			0xff0
+#define L2X0_SAVE_OFFSET1			0xff4
+#define L2X0_AUXCTRL_OFFSET			0xff8
+#define L2X0_PREFETCH_CTRL_OFFSET		0xffc
 
 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04