From patchwork Mon Feb 25 03:49:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2180001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 9AA3E3FCA4 for ; Mon, 25 Feb 2013 03:54:42 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U9p68-0003J4-8T; Mon, 25 Feb 2013 03:51:28 +0000 Received: from mail-da0-f48.google.com ([209.85.210.48]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U9p5n-0003Fm-Tp for linux-arm-kernel@lists.infradead.org; Mon, 25 Feb 2013 03:51:10 +0000 Received: by mail-da0-f48.google.com with SMTP id w4so1250981dam.21 for ; Sun, 24 Feb 2013 19:51:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=VUd2o51wrMNzluM70cpbTyrLAC4d4anrdM/Ced3AicQ=; b=jf1+hw0/g517xPJJqxhXgtGYYANJzrCmV3RUUGdviph9g9Q4gUO5rG1HCg8jZZ5BEH DBgCxdEyZnd6sK/8h8pYukoDybDY+pAaMOBwuita3ULeMzv3PldCW529u/OJLp3dgBlD zAtSEGleBV3zSQ1gc3VPBNbZ8u/kA5p1S5owQ7FqCqoYM8iDUoHr5q2iSxkn0C5WtOpQ MC8IMKd65PrkaR2oYQ1QqZDbxMP4srpX176c0Eo3i7HRqoA9gKQaYXbk+cMrl1TXVWs4 9kxDMbBbIMGqdXUojjW+f53buQQjDe1yWk19D8r/hEqPhHDpYgYvTeno9Q1Hwn2bXI9g 1X1Q== X-Received: by 10.68.129.135 with SMTP id nw7mr15773852pbb.58.1361764266381; Sun, 24 Feb 2013 19:51:06 -0800 (PST) Received: from localhost.localdomain ([67.198.145.34]) by mx.google.com with ESMTPS id b9sm11188695pba.6.2013.02.24.19.51.01 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 24 Feb 2013 19:51:05 -0800 (PST) From: Haojian Zhuang To: grinberg@compulab.co.il, linus.walleij@linaro.org, linux@arm.linux.org.uk, marek.vasut@gmail.com, robert.jarzmik@free.fr, daniel@caiaq.de, linux-arm-kernel@lists.infradead.org, grant.likely@secretlab.ca, cxie4@marvell.com Subject: [PATCH v5 02/12] gpio: pxa: clean code with same variable name Date: Mon, 25 Feb 2013 11:49:31 +0800 Message-Id: <1361764181-26647-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1361764181-26647-1-git-send-email-haojian.zhuang@linaro.org> References: <1361764181-26647-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQlRYbfXv2mB18d2NczeXi6+LZpDJBTJHDdn0rpSAK1dcvGYWGCCpVxA63CU7TxyF568ANS9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130224_225108_997587_FAD7C1D8 X-CRM114-Status: GOOD ( 18.80 ) X-Spam-Score: 0.4 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.48 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Clean code to avoid similar variable. Now use gc for gpio_chip, and use c/chip for pxa_gpio_chip. It's used to avoid confusion. Signed-off-by: Haojian Zhuang --- drivers/gpio/gpio-pxa.c | 113 +++++++++++++++++++++++------------------------ 1 file changed, 55 insertions(+), 58 deletions(-) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 59841b1..ad54392 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -69,20 +69,20 @@ static struct device_node *pxa_gpio_of_node; #endif struct pxa_gpio_chip { - struct gpio_chip chip; - void __iomem *regbase; - char label[10]; + struct gpio_chip gc; + void __iomem *regbase; + char label[10]; - unsigned long irq_mask; - unsigned long irq_edge_rise; - unsigned long irq_edge_fall; - int (*set_wake)(unsigned int gpio, unsigned int on); + unsigned long irq_mask; + unsigned long irq_edge_rise; + unsigned long irq_edge_fall; + int (*set_wake)(unsigned int gpio, unsigned int on); #ifdef CONFIG_PM - unsigned long saved_gplr; - unsigned long saved_gpdr; - unsigned long saved_grer; - unsigned long saved_gfer; + unsigned long saved_gplr; + unsigned long saved_gpdr; + unsigned long saved_grer; + unsigned long saved_gfer; #endif }; @@ -103,9 +103,9 @@ static void __iomem *gpio_reg_base; #define for_each_gpio_chip(i, c) \ for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) -static inline void __iomem *gpio_chip_base(struct gpio_chip *c) +static inline void __iomem *gpio_chip_base(struct gpio_chip *gc) { - return container_of(c, struct pxa_gpio_chip, chip)->regbase; + return container_of(gc, struct pxa_gpio_chip, gc)->regbase; } static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) @@ -141,13 +141,13 @@ static inline int __gpio_is_inverted(int gpio) */ static inline int __gpio_is_occupied(unsigned gpio) { - struct pxa_gpio_chip *pxachip; + struct pxa_gpio_chip *chip; void __iomem *base; unsigned long gafr = 0, gpdr = 0; int ret, af = 0, dir = 0; - pxachip = gpio_to_pxachip(gpio); - base = gpio_chip_base(&pxachip->chip); + chip = gpio_to_pxachip(gpio); + base = gpio_chip_base(&chip->gc); gpdr = readl_relaxed(base + GPDR_OFFSET); switch (gpio_type) { @@ -170,9 +170,9 @@ static inline int __gpio_is_occupied(unsigned gpio) return ret; } -static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +static int pxa_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { - return chip->base + offset + irq_base; + return gc->base + offset + irq_base; } int pxa_irq_to_gpio(int irq) @@ -180,16 +180,16 @@ int pxa_irq_to_gpio(int irq) return irq - irq_base; } -static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +static int pxa_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { - void __iomem *base = gpio_chip_base(chip); + void __iomem *base = gpio_chip_base(gc); uint32_t value, mask = 1 << offset; unsigned long flags; spin_lock_irqsave(&gpio_lock, flags); value = readl_relaxed(base + GPDR_OFFSET); - if (__gpio_is_inverted(chip->base + offset)) + if (__gpio_is_inverted(gc->base + offset)) value |= mask; else value &= ~mask; @@ -199,10 +199,10 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) return 0; } -static int pxa_gpio_direction_output(struct gpio_chip *chip, +static int pxa_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { - void __iomem *base = gpio_chip_base(chip); + void __iomem *base = gpio_chip_base(gc); uint32_t tmp, mask = 1 << offset; unsigned long flags; @@ -211,7 +211,7 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip, spin_lock_irqsave(&gpio_lock, flags); tmp = readl_relaxed(base + GPDR_OFFSET); - if (__gpio_is_inverted(chip->base + offset)) + if (__gpio_is_inverted(gc->base + offset)) tmp &= ~mask; else tmp |= mask; @@ -221,15 +221,15 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip, return 0; } -static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) +static int pxa_gpio_get(struct gpio_chip *gc, unsigned offset) { - return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); + return readl_relaxed(gpio_chip_base(gc) + GPLR_OFFSET) & (1 << offset); } -static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static void pxa_gpio_set(struct gpio_chip *gc, unsigned offset, int value) { - writel_relaxed(1 << offset, gpio_chip_base(chip) + - (value ? GPSR_OFFSET : GPCR_OFFSET)); + writel_relaxed(1 << offset, gpio_chip_base(gc) + + (value ? GPSR_OFFSET : GPCR_OFFSET)); } #ifdef CONFIG_OF_GPIO @@ -240,7 +240,7 @@ static int pxa_gpio_of_xlate(struct gpio_chip *gc, if (gpiospec->args[0] > pxa_last_gpio) return -EINVAL; - if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip) + if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].gc) return -EINVAL; if (flags) @@ -250,42 +250,43 @@ static int pxa_gpio_of_xlate(struct gpio_chip *gc, } #endif -static int pxa_init_gpio_chip(int gpio_end, - int (*set_wake)(unsigned int, unsigned int)) +static int pxa_init_gpio_chip(struct platform_device *pdev, int gpio_end) { int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; struct pxa_gpio_chip *chips; + struct pxa_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); - chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); - if (chips == NULL) { - pr_err("%s: failed to allocate GPIO chips\n", __func__); + chips = devm_kzalloc(&pdev->dev, nbanks * sizeof(*chips), GFP_KERNEL); + if (!chips) { + dev_err(&pdev->dev, "failed to allocate GPIO chips\n"); return -ENOMEM; } for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { - struct gpio_chip *c = &chips[i].chip; + struct gpio_chip *gc = &chips[i].gc; sprintf(chips[i].label, "gpio-%d", i); chips[i].regbase = gpio_reg_base + BANK_OFF(i); - chips[i].set_wake = set_wake; + if (pdata->gpio_set_wake) + chips[i].set_wake = pdata->gpio_set_wake; - c->base = gpio; - c->label = chips[i].label; + gc->base = gpio; + gc->label = chips[i].label; - c->direction_input = pxa_gpio_direction_input; - c->direction_output = pxa_gpio_direction_output; - c->get = pxa_gpio_get; - c->set = pxa_gpio_set; - c->to_irq = pxa_gpio_to_irq; + gc->direction_input = pxa_gpio_direction_input; + gc->direction_output = pxa_gpio_direction_output; + gc->get = pxa_gpio_get; + gc->set = pxa_gpio_set; + gc->to_irq = pxa_gpio_to_irq; #ifdef CONFIG_OF_GPIO - c->of_node = pxa_gpio_of_node; - c->of_xlate = pxa_gpio_of_xlate; - c->of_gpio_n_cells = 2; + gc->of_node = pxa_gpio_of_node; + gc->of_xlate = pxa_gpio_of_xlate; + gc->of_gpio_n_cells = 2; #endif /* number of GPIOs on last bank may be less than 32 */ - c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; - gpiochip_add(c); + gc->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; + gpiochip_add(gc); } pxa_gpio_chips = chips; return 0; @@ -364,7 +365,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) do { loop = 0; for_each_gpio_chip(gpio, c) { - gpio_base = c->chip.base; + gpio_base = c->gc.base; gedr = readl_relaxed(c->regbase + GEDR_OFFSET); gedr = gedr & c->irq_mask; @@ -492,7 +493,7 @@ const struct irq_domain_ops pxa_irq_domain_ops = { static int pxa_gpio_probe_dt(struct platform_device *pdev) { - int ret, nr_banks, nr_gpios; + int nr_banks, nr_gpios; struct pxa_gpio_platform_data *pdata; struct device_node *prev, *next, *np = pdev->dev.of_node; const struct of_device_id *of_id = @@ -514,8 +515,7 @@ static int pxa_gpio_probe_dt(struct platform_device *pdev) prev = next; if (!next) { dev_err(&pdev->dev, "Failed to find child gpio node\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } for (nr_banks = 1; ; nr_banks++) { next = of_get_next_child(np, prev); @@ -530,15 +530,12 @@ static int pxa_gpio_probe_dt(struct platform_device *pdev) irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); if (irq_base < 0) { dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); - goto err; + return -EINVAL; } domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, &pxa_irq_domain_ops, NULL); pxa_gpio_of_node = np; return 0; -err: - iounmap(gpio_reg_base); - return ret; } #else #define pxa_gpio_probe_dt(pdev) (-1) @@ -603,7 +600,7 @@ static int pxa_gpio_probe(struct platform_device *pdev) /* Initialize GPIO chips */ info = dev_get_platdata(&pdev->dev); - pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); + pxa_init_gpio_chip(pdev, pxa_last_gpio); /* clear all GPIO edge detects */ for_each_gpio_chip(gpio, c) {