From patchwork Wed Feb 27 10:36:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 2192761 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C96B73FD4E for ; Wed, 27 Feb 2013 10:40:18 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UAeN9-0002st-WD; Wed, 27 Feb 2013 10:36:28 +0000 Received: from mail-da0-f42.google.com ([209.85.210.42]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UAeN7-0002sa-7V for linux-arm-kernel@lists.infradead.org; Wed, 27 Feb 2013 10:36:26 +0000 Received: by mail-da0-f42.google.com with SMTP id n15so238970dad.1 for ; Wed, 27 Feb 2013 02:36:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=YTD8vSngRhUBsK3/jxpoJkYQND2MfMkX7Wezs8cfRtQ=; b=DM2z1nCPVyUUOgHLPqF46MqzSfvPGwP0EQhdCRB/yhzkCNviS7NKqZ2lx/kZa33cXs w8c/8DiKHvt5XGDOWDwH2x/QoZE+Li8Z15cocawuU3rhOaQCf1h8BjEwj6wpt/+W4u7Y BsIGW1GiGFdhrnOKtGXSVuLP9rcV5vyfKXvvKZr3vokutnkaQJGaNSSXE2dnZYlpm9Y0 ADMTva/Ilhhvjz1eiYUq4nFE/GaW9cRVNU91kdCj+VikZHb/cL2U95DCRMErXbb3JX0U kuJ9y7uAJX9eJK2mlSx024cYiHwnh8Y4y1UsWvROATljOMfZTW8jFu2WFCGAyOKW6hsT Trpg== X-Received: by 10.66.250.169 with SMTP id zd9mr6830641pac.134.1361961382498; Wed, 27 Feb 2013 02:36:22 -0800 (PST) Received: from inder-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id w2sm4917406pax.22.2013.02.27.02.36.19 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 02:36:21 -0800 (PST) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] arm: plat-samsung: check processor type before cache restoration in resume Date: Wed, 27 Feb 2013 16:06:03 +0530 Message-Id: <1361961363-28412-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQnrrmtTvylpqQN5Pzrs3iLEWuo++qJl9rDHwl9nzSmmV2jwSqChNkr0cQrcDFJ478Ou9Fgp X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130227_053625_358697_C9474F55 X-CRM114-Status: GOOD ( 10.73 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.42 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, linux@arm.linux.org.uk, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh --- changes in v2: - check processor midr instead of checking all soc ids as suggested by Kukjin changes in v3: - simplify by reading midr in assembly as per Russell arch/arm/plat-samsung/s5p-sleep.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dad..6e15993 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,9 @@ #include #include +#define CPU_MASK 0xff0ffff0 +#define CPU_CORTEX_A9 0x410fc090 + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +54,12 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =CPU_MASK + and r0, r0, r1 + ldr r1, =CPU_CORTEX_A9 + cmp r0, r1 + bne resume_l2on adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE]