From patchwork Tue Mar 5 03:47:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 2216991 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id DE853DF24C for ; Tue, 5 Mar 2013 04:00:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCj0P-0002w7-N4; Tue, 05 Mar 2013 03:57:33 +0000 Received: from inca-roads.misterjones.org ([213.251.177.50]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCixn-0001A6-2i for linux-arm-kernel@lists.infradead.org; Tue, 05 Mar 2013 03:54:52 +0000 Received: from [118.143.64.134] (helo=why.wild-wind.fr.eu.org) by inca-roads.misterjones.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1UCirW-0002NK-Oi; Tue, 05 Mar 2013 04:48:23 +0100 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Subject: [PATCH 10/29] arm64: KVM: Cortex-A57 specific system registers handling Date: Tue, 5 Mar 2013 03:47:26 +0000 Message-Id: <1362455265-24165-11-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1362455265-24165-1-git-send-email-marc.zyngier@arm.com> References: <1362455265-24165-1-git-send-email-marc.zyngier@arm.com> X-SA-Exim-Connect-IP: 118.143.64.134 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, catalin.marinas@arm.com X-SA-Exim-Mail-From: marc.zyngier@arm.com X-SA-Exim-Scanned: No (on inca-roads.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130304_225451_329768_34DAF85D X-CRM114-Status: GOOD ( 15.83 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: catalin.marinas@arm.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the support code for Cortex-A57 specific system registers. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs_a57.c | 96 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 arch/arm64/kvm/sys_regs_a57.c diff --git a/arch/arm64/kvm/sys_regs_a57.c b/arch/arm64/kvm/sys_regs_a57.c new file mode 100644 index 0000000..dcc88fe --- /dev/null +++ b/arch/arm64/kvm/sys_regs_a57.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2012 - ARM Ltd + * Author: Marc Zyngier + * + * Based on arch/arm/kvm/coproc_a15.c: + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Authors: Rusty Russell + * Christoffer Dall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sys_regs.h" + +#define MPIDR_EL1_AFF0_MASK 0xff + +static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + /* + * Simply map the vcpu_id into the Aff0 field of the MPIDR. + */ + vcpu->arch.sys_regs[MPIDR_EL1] = (1 << 31) | (vcpu->vcpu_id & MPIDR_EL1_AFF0_MASK); +} + +static bool access_actlr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt) = vcpu->arch.sys_regs[ACTLR_EL1]; + return true; +} + +static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u64 actlr; + + asm volatile("mrs %0, actlr_el1\n" : "=r" (actlr)); + vcpu->arch.sys_regs[ACTLR_EL1] = actlr; +} + +/* + * A57-specific sys-reg registers. + * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 + */ +static const struct sys_reg_desc a57_sys_regs[] = { + { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101), /* MPIDR_EL1 */ + NULL, reset_mpidr, MPIDR_EL1 }, + { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000), /* SCTLR_EL1 */ + NULL, reset_val, SCTLR_EL1, 0x00C50078 }, + { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001), /* ACTLR_EL1 */ + access_actlr, reset_actlr, ACTLR_EL1 }, + { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010), /* CPACR_EL1 */ + NULL, reset_val, CPACR_EL1, 0 }, +}; + +static struct kvm_sys_reg_target_table a57_target_table = { + .target = KVM_ARM_TARGET_CORTEX_A57, + .table64 = { + .table = a57_sys_regs, + .num = ARRAY_SIZE(a57_sys_regs), + }, +}; + +static int __init sys_reg_a57_init(void) +{ + unsigned int i; + + for (i = 1; i < ARRAY_SIZE(a57_sys_regs); i++) + BUG_ON(cmp_sys_reg(&a57_sys_regs[i-1], + &a57_sys_regs[i]) >= 0); + + kvm_register_target_sys_reg_table(&a57_target_table); + return 0; +} +late_initcall(sys_reg_a57_init);