From patchwork Wed Mar 6 13:43:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 2226111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id D2CC93FC8A for ; Wed, 6 Mar 2013 13:49:09 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UDEf2-0008SB-9m; Wed, 06 Mar 2013 13:45:37 +0000 Received: from mail.free-electrons.com ([94.23.35.102]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UDEds-0007ux-3x for linux-arm-kernel@lists.infradead.org; Wed, 06 Mar 2013 13:44:25 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 37A312A9E; Wed, 6 Mar 2013 14:44:25 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (unknown [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 2A8241209; Wed, 6 Mar 2013 14:44:00 +0100 (CET) From: Thomas Petazzoni To: Jason Cooper , Andrew Lunn , Gregory Clement Subject: [PATCH 02/10] arm: plat-orion: use mv_mbus_dram_info() in PCIe code Date: Wed, 6 Mar 2013 14:43:38 +0100 Message-Id: <1362577426-12804-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1362577426-12804-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1362577426-12804-1-git-send-email-thomas.petazzoni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130306_084424_329333_21F23CA8 X-CRM114-Status: GOOD ( 12.20 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Lior Amsalem , Arnd Bergmann , Maen Suleiman , Ezequiel Garcia , Olof Johansson , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The PCIe code was directly accessing the orion_mbus_dram_info structure to get access to a description of the SDRAM chip selects in order to configure the PCIe -> SDRAM address decoding windows. However, with the introduction of the orion-mbus driver, we are going to remove this global structure and instead leave only the exported mv_mbus_dram_info() function to access this description of the SDRAM chip selects. Therefore, we simply switch to using this API. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/pcie.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index f20a321..8b8c06d 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base) * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks * WIN[0-3] -> DRAM bank[0-3] */ -static void __init orion_pcie_setup_wins(void __iomem *base, - struct mbus_dram_target_info *dram) +static void __init orion_pcie_setup_wins(void __iomem *base) { + const struct mbus_dram_target_info *dram; u32 size; int i; + dram = mv_mbus_dram_info(); + /* * First, disable and clear BARs and windows. */ @@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, */ size = 0; for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; + const struct mbus_dram_window *cs = dram->cs + i; writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); writel(0, base + PCIE_WIN04_REMAP_OFF(i)); @@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base) /* * Point PCIe unit MBUS decode windows to DRAM space. */ - orion_pcie_setup_wins(base, &orion_mbus_dram_info); + orion_pcie_setup_wins(base); /* * Master + slave enable.