| Message ID | 1362852678-13421-5-git-send-email-ldewangan@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 03/09/2013 11:11 AM, Laxman Dewangan wrote: > NVIDIA's Tegra114 SoCs have the matrix keyboard controller which > supports 11x8 type of matrix. The number of rows and columns > are configurable. > > Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc", > "nvidia,tegra20-kbc". I thought the HW really wasn't compatible with Tegra20 due to the reduced number of rows/columns/pins supported?
On Monday 11 March 2013 11:13 PM, Stephen Warren wrote: > On 03/09/2013 11:11 AM, Laxman Dewangan wrote: >> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which >> supports 11x8 type of matrix. The number of rows and columns >> are configurable. >> >> Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc", >> "nvidia,tegra20-kbc". > I thought the HW really wasn't compatible with Tegra20 due to the > reduced number of rows/columns/pins supported? Hw controller is really compatible. Only thing is that there is no physical pins on SoC for KBC-ROW11 to KBC-ROW15. Because, there is no physical pins for ROW11 to ROW15, we asked to remove programming/reference this rows from TRM of T114 to consistent with SoCs.
On 03/11/2013 11:59 AM, Laxman Dewangan wrote: > On Monday 11 March 2013 11:13 PM, Stephen Warren wrote: >> On 03/09/2013 11:11 AM, Laxman Dewangan wrote: >>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which >>> supports 11x8 type of matrix. The number of rows and columns >>> are configurable. >>> >>> Add DT entry for KBC controller with compatibility as >>> "nvidia,tegra114-kbc", >>> "nvidia,tegra20-kbc". >> I thought the HW really wasn't compatible with Tegra20 due to the >> reduced number of rows/columns/pins supported? > > Hw controller is really compatible. Only thing is that there is no > physical pins on SoC for KBC-ROW11 to KBC-ROW15. > Because, there is no physical pins for ROW11 to ROW15, we asked to > remove programming/reference this rows from TRM of T114 to consistent > with SoCs. I think that makes the HW incompatible. If you only have knowledge of Tegra20/30, you can assume that there are more rows/pins/columns than there actually are. Applying those same validation restrictions on Tegra114 will yield validation that isn't strict enough; invalid values could be accepted.
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 300082d..21ff340 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -248,6 +248,14 @@ clocks = <&tegra_car 4>; }; + kbc { + compatible = "nvidia,tegra114-kbc", "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = <0 85 0x04>; + clocks = <&tegra_car 36>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>;
NVIDIA's Tegra114 SoCs have the matrix keyboard controller which supports 11x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc", "nvidia,tegra20-kbc". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- Changes from V1: - Add compatible for kbc as nvidia,tegra114-kbc and nvidia,tegra20-kbc. arch/arm/boot/dts/tegra114.dtsi | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)