From patchwork Sat Mar 9 20:23:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2242571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 7F294DF2F2 for ; Sat, 9 Mar 2013 20:34:49 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UEQPH-0007GA-5Y; Sat, 09 Mar 2013 20:30:17 +0000 Received: from mail-wi0-x22a.google.com ([2a00:1450:400c:c05::22a]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UEQJJ-0004UB-3J for linux-arm-kernel@lists.infradead.org; Sat, 09 Mar 2013 20:24:13 +0000 Received: by mail-wi0-f170.google.com with SMTP id hm11so349847wib.5 for ; Sat, 09 Mar 2013 12:24:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=D+EmjrifnlWE58Iafms0+8wzk7vHoOmA7C0WZnhoLHs=; b=pcgC/65ggmVzm+R2xzB9wWtd0smAIZMFPy8fZmofWxxq7LxWv1Y3VBDDkN9+6aoYXX imc4VYWN9cZCNqLBnIRA/nhDKErypWp+ZZ8Z9uPf+gYfYWgjUFjcnJzgbSYSO+T7uNIG Q/+C6VzBFBrRHHBRCsboZxe/i2yWIwtn8XSKkXL32FYKiZDfLPWhW9TFtwQL1VP0+xs0 Ak2Sd3GFINxIvsUoZA4LYALMCoGf6/5hIom90C9ChVOzxXyEDx/y1PYbtjBhT/lSVnlc AqJPpkEV2NJSN1YYBKu03aaKNee4JsIdrHy97doT7VZODkNjtVVtV7LWw6Db9nWBugIv h42g== X-Received: by 10.194.235.196 with SMTP id uo4mr11196361wjc.30.1362860642927; Sat, 09 Mar 2013 12:24:02 -0800 (PST) Received: from flatron.tomeq (87-207-52-162.dynamic.chello.pl. [87.207.52.162]) by mx.google.com with ESMTPS id ed6sm6858911wib.9.2013.03.09.12.24.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 09 Mar 2013 12:24:02 -0800 (PST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 12/12] clocksource: samsung-time: Add Device Tree support Date: Sat, 9 Mar 2013 21:23:21 +0100 Message-Id: <1362860601-18464-13-git-send-email-tomasz.figa@gmail.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1362860601-18464-1-git-send-email-tomasz.figa@gmail.com> References: <1362860601-18464-1-git-send-email-tomasz.figa@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130309_152405_847899_B77D3A90 X-CRM114-Status: GOOD ( 17.92 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (tomasz.figa[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: ghcstop@gmail.com, Mark Rutland , Kukjin Kim , linux@arm.linux.org.uk, =?UTF-8?q?Heiko=20St=C3=BCbner?= , kwangwoo.lee@gmail.com, devicetree-discuss@lists.ozlabs.org, broonie@opensource.wolfsonmicro.com, mcuelenaere@gmail.com, Tomasz Figa , christer@weinigel.se, kyungmin.park@samsung.com, linux-samsung-soc@vger.kernel.org, buserror@gmail.com, augulis.darius@gmail.com, jacmet@sunsite.dk, Sylwester Nawrocki , linux@simtec.co.uk, jekhor@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds support for parsing all platform-specific data from Device Tree and instantiation using clocksource_of_init to samsung-time clocksource driver. Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Tomasz Figa --- .../devicetree/bindings/timer/samsung-pwm.txt | 33 ++++++ drivers/clocksource/samsung-time.c | 116 ++++++++++++++++++++- 2 files changed, 146 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/samsung-pwm.txt diff --git a/Documentation/devicetree/bindings/timer/samsung-pwm.txt b/Documentation/devicetree/bindings/timer/samsung-pwm.txt new file mode 100644 index 0000000..3aabe81 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/samsung-pwm.txt @@ -0,0 +1,33 @@ +* Samsung PWM timers + +Samsung SoCs contain PWM timer blocks which can be used for system clock source +and clock event timers. + +Be aware that this configuration is supported only on uniprocessor platforms. +For SMP SoCs, SMP-aware timers should be used, like MCT. + +Required properties: +- compatible : should be one of following: + samsung,s3c24xx-pwm - for 16-bit timers present on S3C24xx + samsung,s3c64xx-pwm - for 32-bit timers present on S3C64xx and newer +- reg: base address and size of register area +- interrupts: list of timer interrupts (one interrupt per timer, starting at + timer 0) + +Optional properties: +- samsung,prescale-divisor: PWM prescaler divisor (from 1 to 256) +- samsung,divisor: PWM main divider divisor (1, 2, 4, 8 or 16) +- samsung,pwm-outputs: list of PWM channels reserved for use as PWM outputs + - an array of up to 5 elements being indices of PWM channels (from 0 to 4), + the order does not matter. + +Example: + timer@7f006000 { + compatible = "samsung,s3c64xx-pwm"; + reg = <0x7f006000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <23>, <24>, <25>, <27>, <28>; + samsung,prescale-divisor = <2>; + samsung,divisor = <1>; + samsung,pwm-outputs = <0>, <1>; + }; diff --git a/drivers/clocksource/samsung-time.c b/drivers/clocksource/samsung-time.c index 5c6cfca..dbfc5f2 100644 --- a/drivers/clocksource/samsung-time.c +++ b/drivers/clocksource/samsung-time.c @@ -14,6 +14,9 @@ #include #include #include +#include +#include +#include #include #include @@ -412,9 +415,12 @@ static void __init samsung_timer_resources(void) unsigned long source_id = timer_source.source_id; char devname[15]; - timer_base = ioremap_nocache(timer_variant.reg_base, SZ_4K); - if (!timer_base) - panic("failed to map timer registers"); + if (!timer_base) { + /* Compatibility fallback for non-DT platforms */ + timer_base = ioremap_nocache(timer_variant.reg_base, SZ_4K); + if (!timer_base) + panic("failed to map timer registers"); + } timerclk = clk_get(NULL, "timers"); if (IS_ERR(timerclk)) @@ -447,6 +453,11 @@ static void __init samsung_timer_resources(void) clk_enable(tin_source); } +enum { + TYPE_S3C24XX, + TYPE_S3C64XX, +}; + void __init samsung_timer_init(void) { if (!timer_source.source_id && !timer_source.event_id) @@ -459,3 +470,102 @@ void __init samsung_timer_init(void) samsung_clockevent_init(); samsung_clocksource_init(); } + +#ifdef CONFIG_OF +static const struct of_device_id samsung_timer_ids[] = { + { .compatible = "samsung,s3c24xx-pwm", .data = (void *)TYPE_S3C24XX, }, + { .compatible = "samsung,s3c64xx-pwm", .data = (void *)TYPE_S3C64XX, }, + {}, +}; + +static void __init samsung_of_timer_init(void) +{ + const struct of_device_id *match; + u8 channel_mask = (1 << 5) - 1; + struct device_node *np; + struct property *prop; + const __be32 *cur; + u32 val; + int i; + + np = of_find_matching_node_and_match(NULL, + samsung_timer_ids, &match); + if (!np) + panic("timer node not found"); + + timer_base = of_iomap(np, 0); + if (!timer_base) + panic("failed to map timer registers"); + + for (i = 0; i < SAMSUNG_PWM_NUM; ++i) + timer_variant.irqs[i] = irq_of_parse_and_map(np, i); + + if (!timer_variant.irqs[timer_source.event_id]) + panic("no clock event irq provided"); + + switch ((unsigned int)match->data) { + case TYPE_S3C24XX: + timer_variant.bits = 16; + timer_variant.prescale = 25; + timer_variant.divisor = 2; + timer_variant.has_tint_cstat = false; + break; + case TYPE_S3C64XX: + timer_variant.bits = 32; + timer_variant.prescale = 2; + timer_variant.divisor = 1; + timer_variant.has_tint_cstat = true; + break; + } + + of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { + if (val >= SAMSUNG_PWM_NUM) { + pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n", + __func__); + continue; + } + channel_mask &= ~(1 << val); + } + + val = fls(channel_mask); + if (!val) + panic("failed to find PWM channel for clock source"); + timer_source.source_id = val - 1; + channel_mask &= ~(1 << timer_source.source_id); + + val = fls(channel_mask); + if (!val) + panic("failed to find PWM channel for clock events"); + timer_source.event_id = val - 1; + + if (!of_property_read_u32(np, "samsung,prescale-divisor", &val)) { + if (val < 1 || val > 256) + panic("samsung,prescale-divisor property out of range"); + timer_variant.prescale = val; + } + + if (!of_property_read_u32(np, "samsung,divisor", &val)) { + switch (val) { + case 1: + case 2: + case 4: + case 8: + case 16: + timer_variant.divisor = val; + break; + default: + panic("invalid value of samsung,divisor property"); + } + } + + pr_info("samsung-time: using PWM channels %d (source) and %d (event)\n", + timer_source.source_id, timer_source.event_id); + + samsung_timer_init(); +} +#endif /* CONFIG_OF */ + +CLOCKSOURCE_OF_DECLARE(s3c24xx_timer, + "samsung,s3c24xx-pwm", samsung_of_timer_init) +CLOCKSOURCE_OF_DECLARE(s3c64xx_timer, + "samsung,s3c64xx-pwm", samsung_of_timer_init)