From patchwork Wed Mar 13 21:55:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2265091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C24BA3FD8C for ; Wed, 13 Mar 2013 21:56:58 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UFtcx-0005nK-Vf; Wed, 13 Mar 2013 21:54:27 +0000 Received: from mail-db8lp0187.outbound.messaging.microsoft.com ([213.199.154.187] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UFtcj-0005lq-6t for linux-arm-kernel@lists.infradead.org; Wed, 13 Mar 2013 21:54:14 +0000 Received: from mail132-db8-R.bigfish.com (10.174.8.248) by DB8EHSOBE015.bigfish.com (10.174.4.78) with Microsoft SMTP Server id 14.1.225.23; Wed, 13 Mar 2013 21:54:11 +0000 Received: from mail132-db8 (localhost [127.0.0.1]) by mail132-db8-R.bigfish.com (Postfix) with ESMTP id 54ED81E00C9; Wed, 13 Mar 2013 21:54:11 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received-SPF: pass (mail132-db8: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail132-db8 (localhost.localdomain [127.0.0.1]) by mail132-db8 (MessageSwitch) id 1363211649775187_11106; Wed, 13 Mar 2013 21:54:09 +0000 (UTC) Received: from DB8EHSMHS021.bigfish.com (unknown [10.174.8.243]) by mail132-db8.bigfish.com (Postfix) with ESMTP id B0E4648004A; Wed, 13 Mar 2013 21:54:09 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB8EHSMHS021.bigfish.com (10.174.4.31) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 13 Mar 2013 21:54:07 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Wed, 13 Mar 2013 14:44:54 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r2DLs1x7027216; Wed, 13 Mar 2013 14:54:05 -0700 (PDT) From: To: Subject: [PATCHv1 1/2] ARM: socfpga: Enable hotplug and soft reset Date: Wed, 13 Mar 2013 16:55:21 -0500 Message-ID: <1363211722-27237-2-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363211722-27237-1-git-send-email-dinguyen@altera.com> References: <1363211722-27237-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130313_175413_478888_6D639B59 X-CRM114-Status: GOOD ( 12.11 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [213.199.154.187 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: dinh.linux@gmail.com, arnd@arndb.de, pavel@denx.de, Dinh Nguyen , olof@lixom.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Dinh Nguyen Put CPU1 into reset when it is hotplugged. Enable a cold or warm reset to the HW from userspace. Also fix a few sparse errors: warning: symbol 'sys_manager_base_addr' was not declared. Should it be static? warning: symbol 'rst_manager_base_addr' was not declared. Should it be static? Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/core.h | 17 +++++++++++++++++ arch/arm/mach-socfpga/platsmp.c | 9 ++++++--- arch/arm/mach-socfpga/socfpga.c | 10 +++++++++- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 315edff..d2a251f 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -20,12 +20,29 @@ #ifndef __MACH_CORE_H #define __MACH_CORE_H +#define SOCFPGA_RSTMGR_CTRL 0x04 +#define SOCFPGA_RSTMGR_MODPERRST 0x14 +#define SOCFPGA_RSTMGR_BRGMODRST 0x1c + +/* System Manager bits */ +#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ +#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ +/*MPU Module Reset Register */ +#define RSTMGR_MPUMODRST_CPU0 0x1 /*CPU0 Reset*/ +#define RSTMGR_MPUMODRST_CPU1 0x2 /*CPU1 Reset*/ +#define RSTMGR_MPUMODRST_WDS 0x4 /*Watchdog Reset*/ +#define RSTMGR_MPUMODRST_SCUPER 0x8 /*SCU and periphs reset*/ +#define RSTMGR_MPUMODRST_L2 0x10 /*L2 Cache reset*/ + extern void socfpga_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; extern void socfpga_init_clocks(void); extern void socfpga_sysmgr_init(void); +extern void __iomem *sys_manager_base_addr; +extern void __iomem *rst_manager_base_addr; + extern struct smp_operations socfpga_smp_ops; extern char secondary_trampoline, secondary_trampoline_end; diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 84c60fa..c75c33d 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -30,9 +30,6 @@ #include "core.h" -extern void __iomem *sys_manager_base_addr; -extern void __iomem *rst_manager_base_addr; - static void __cpuinit socfpga_secondary_init(unsigned int cpu) { /* @@ -100,6 +97,12 @@ static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus) */ static void socfpga_cpu_die(unsigned int cpu) { + /* Flush the L1 data cache. */ + flush_cache_all(); + + /* This will put CPU1 into reset.*/ + __raw_writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + 0x10); + cpu_do_idle(); /* We should have never returned from idle */ diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 1042c02..b41a945 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -87,7 +87,15 @@ static void __init socfpga_init_irq(void) static void socfpga_cyclone5_restart(char mode, const char *cmd) { - /* TODO: */ + u32 temp; + + temp = __raw_readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); + + if (mode == 'h') + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; + else + temp |= RSTMGR_CTRL_SWWARMRSTREQ; + __raw_writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } static void __init socfpga_cyclone5_init(void)