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[93.74.62.0]) by mx.google.com with ESMTPS id h7sm180032lbp.16.2013.03.13.17.11.56 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 13 Mar 2013 17:11:57 -0700 (PDT) From: Ruslan Bilovol To: tony@atomide.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Subject: [PATCH RESEND 1/1] omap4: control: Add the CONTROL_SMART2IO_PADCONF_2 register definition Date: Thu, 14 Mar 2013 02:11:48 +0200 Message-Id: <1363219908-32007-2-git-send-email-ruslan.bilovol@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363219908-32007-1-git-send-email-ruslan.bilovol@ti.com> References: <1363219908-32007-1-git-send-email-ruslan.bilovol@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130313_201200_674745_BF10FAEE X-CRM114-Status: UNSURE ( 8.28 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.217.169 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (ruslan.bilovol[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds missing CONTROL_SMART2IO_PADCONF_2 register definition Signed-off-by: Ruslan Bilovol --- arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h index c88420d..d512ade 100644 --- a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h @@ -46,6 +46,7 @@ #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2 0x05cc #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 @@ -764,6 +765,50 @@ #define OMAP4_HSI_DR0_LB_SHIFT 10 #define OMAP4_HSI_DR0_LB_MASK (1 << 10) +/* CONTROL_SMART2IO_PADCONF_2 */ +#define OMAP4_DPM_DR1_DS_SHIFT 31 +#define OMAP4_DPM_DR1_DS_MASK (1 << 31) +#define OMAP4_DPM_DR2_DS_SHIFT 30 +#define OMAP4_DPM_DR2_DS_MASK (1 << 30) +#define OMAP4_DPM_DR3_DS_SHIFT 29 +#define OMAP4_DPM_DR3_DS_MASK (1 << 29) +#define OMAP4_GPIO_DR10_DS_SHIFT 28 +#define OMAP4_GPIO_DR10_DS_MASK (1 << 28) +#define OMAP4_HSI2_DR0_DS_SHIFT 27 +#define OMAP4_HSI2_DR0_DS_MASK (1 << 27) +#define OMAP4_HSI2_DR1_DS_SHIFT 26 +#define OMAP4_HSI2_DR1_DS_MASK (1 << 26) +#define OMAP4_HSI2_DR2_DS_SHIFT 25 +#define OMAP4_HSI2_DR2_DS_MASK (1 << 25) +#define OMAP4_SDMMC3_DR0_DS_SHIFT 24 +#define OMAP4_SDMMC3_DR0_DS_MASK (1 << 24) +#define OMAP4_SDMMC4_DR0_DS_SHIFT 23 +#define OMAP4_SDMMC4_DR0_DS_MASK (1 << 23) +#define OMAP4_SDMMC4_DR1_DS_SHIFT 22 +#define OMAP4_SDMMC4_DR1_DS_MASK (1 << 22) +#define OMAP4_SPI3_DR0_DS_SHIFT 21 +#define OMAP4_SPI3_DR0_DS_MASK (1 << 21) +#define OMAP4_SPI3_DR1_DS_SHIFT 20 +#define OMAP4_SPI3_DR1_DS_MASK (1 << 20) +#define OMAP4_UART3_DR2_DS_SHIFT 19 +#define OMAP4_UART3_DR2_DS_MASK (1 << 19) +#define OMAP4_UART3_DR3_DS_SHIFT 18 +#define OMAP4_UART3_DR3_DS_MASK (1 << 18) +#define OMAP4_UART3_DR4_DS_SHIFT 17 +#define OMAP4_UART3_DR4_DS_MASK (1 << 17) +#define OMAP4_UART3_DR5_DS_SHIFT 16 +#define OMAP4_UART3_DR5_DS_MASK (1 << 16) +#define OMAP4_USBA0_DR0_DS_SHIFT 15 +#define OMAP4_USBA0_DR0_DS_MASK (1 << 15) +#define OMAP4_USBA0_DR1_DS_SHIFT 14 +#define OMAP4_USBA0_DR1_DS_MASK (1 << 14) +#define OMAP4_USBA_DR2_DS_SHIFT 13 +#define OMAP4_USBA_DR2_DS_MASK (1 << 13) +#define OMAP4_USBB2_DR0_DS_SHIFT 12 +#define OMAP4_USBB2_DR0_DS_MASK (1 << 12) +#define OMAP4_USBB1_DR0_DS_SHIFT 11 +#define OMAP4_USBB1_DR0_DS_MASK (1 << 11) + /* CONTROL_USBB_HSIC */ #define OMAP4_USBB2_DR1_SR_SHIFT 30 #define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)