From patchwork Mon Mar 18 14:00:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerlando Falauto X-Patchwork-Id: 2293511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id ED8CB3FCF6 for ; Mon, 18 Mar 2013 15:17:06 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UHbkb-0000bL-Hc; Mon, 18 Mar 2013 15:13:25 +0000 Received: from mail-de.keymile.com ([195.8.104.1]) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UHaco-0007Fd-Hu for linux-arm-kernel@lists.infradead.org; Mon, 18 Mar 2013 14:01:23 +0000 Received: from mailrelay.de.keymile.net ([10.9.1.54]) by eSafe SMTP Relay 1363609782; Mon, 18 Mar 2013 15:01:15 +0100 Received: from chber1-10555x.ch.keymile.net ([172.31.40.82]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r2IDxIsL027459; Mon, 18 Mar 2013 14:59:28 +0100 (MET) From: Gerlando Falauto To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 7/9] genirq: handle separate mask registers Date: Mon, 18 Mar 2013 15:00:53 +0100 Message-Id: <1363615255-18200-8-git-send-email-gerlando.falauto@keymile.com> X-Mailer: git-send-email 1.7.10.1 In-Reply-To: <1363615255-18200-1-git-send-email-gerlando.falauto@keymile.com> References: <1363277430-21325-1-git-send-email-holger.brunck@keymile.com><1363615255-18200-1-git-send-email-gerlando.falauto@keymile.com> X-ESAFE-STATUS: [srvhellgate.de.keymile.net] Mail allowed X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130318_100118_951004_D6425748 X-CRM114-Status: GOOD ( 11.20 ) X-Spam-Score: -5.1 (-----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-5.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [195.8.104.1 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Andrew Lunn , Jason Cooper , Nicolas Pitre , Holger Brunck , Gerlando Falauto , Ben Dooks , Thomas Gleixner , Joey Oravec , Simon Guinot , Lennert Buytenhek X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There are cases where all irq_chip_type instances have separate mask registers, making a shared mask register cache unsuitable for the purpose. So introduce a new flag IRQ_GC_SEPARATE_MASK_REGISTERS to explicitly enable this separate treatment. When this flag is not set, pointers for all irq_chip_type instances point to the the shared mask register as it has been done so far. Signed-off-by: Gerlando Falauto --- include/linux/irq.h | 1 + kernel/irq/generic-chip.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/linux/irq.h b/include/linux/irq.h index 5aca310..9feb06f 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -700,6 +700,7 @@ struct irq_chip_generic { enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1 << 0, IRQ_GC_INIT_NESTED_LOCK = 1 << 1, + IRQ_GC_SEPARATE_MASK_REGISTERS = 1 << 2, }; /* Generic chip callback functions */ diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index b5cb991..ae5ce41 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -241,19 +241,26 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, { struct irq_chip_type *ct = gc->chip_types; unsigned int i; + bool mskperct = flags & IRQ_GC_SEPARATE_MASK_REGISTERS; + bool mskinit = flags & IRQ_GC_INIT_MASK_CACHE; raw_spin_lock(&gc_lock); list_add_tail(&gc->list, &gc_list); raw_spin_unlock(&gc_lock); /* Init mask cache ? */ - if (flags & IRQ_GC_INIT_MASK_CACHE) + if (mskinit && !mskperct) gc->shared_mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask); - /* Initialize mask cache pointer */ - for (i = 0; i < gc->num_ct; i++) - ct[i].pmask_cache = &gc->shared_mask_cache; + /* Initialize mask cache pointers */ + for (i = 0; i < gc->num_ct; i++) { + ct[i].pmask_cache = mskperct ? + &ct[i].mask_cache : &gc->shared_mask_cache; + if (mskinit && mskperct) + ct[i].mask_cache = + irq_reg_readl(gc->reg_base + ct[i].regs.mask); + } for (i = gc->irq_base; msk; msk >>= 1, i++) { if (!(msk & 0x01))