From patchwork Fri Mar 22 12:02:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 2319191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 16EDDDFE82 for ; Fri, 22 Mar 2013 12:06:14 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UJ0gh-0006a5-1H; Fri, 22 Mar 2013 12:03:11 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UJ0ge-0006Zi-1P for linux-arm-kernel@lists.infradead.org; Fri, 22 Mar 2013 12:03:08 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 22 Mar 2013 05:08:27 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 22 Mar 2013 05:02:58 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 22 Mar 2013 05:02:58 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 22 Mar 2013 05:03:02 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 22 Mar 2013 05:03:02 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r2MC2xlD011421; Fri, 22 Mar 2013 05:03:00 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver Subject: [PATCH] clk: tegra: Don't enable PLLs during early boot Date: Fri, 22 Mar 2013 14:02:33 +0200 Message-ID: <1363953762-29783-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130322_080308_248858_89F39B91 X-CRM114-Status: GOOD ( 10.66 ) X-Spam-Score: -9.4 (---------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-9.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -2.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Prashant Gaikwad , Mike Turquette , Stephen Warren , Thierry Reding , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The PLL code relies on udelay() which is not available when CCF is initialized. Hence we can't enable any PLL during this phase. Signed-off-by: Peter De Schrijver --- Stephen, Can you confirm this is ok for the audio drivers? We used to be lucky that this has worked up to now, but I will introduce some changes to the pll lock check code which cause this to fail due to the slight differences in timing. --- drivers/clk/tegra/clk-tegra20.c | 4 ++-- drivers/clk/tegra/clk-tegra30.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index b92d48b..7cc76b0 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1230,8 +1230,8 @@ static __initdata struct tegra_clk_init_table init_table[] = { {usbd, clk_max, 12000000, 0}, {usb2, clk_max, 12000000, 0}, {usb3, clk_max, 12000000, 0}, - {pll_a, clk_max, 56448000, 1}, - {pll_a_out0, clk_max, 11289600, 1}, + {pll_a, clk_max, 56448000, 0}, + {pll_a_out0, clk_max, 11289600, 0}, {cdev1, clk_max, 0, 1}, {blink, clk_max, 32768, 1}, {i2s1, pll_a_out0, 11289600, 0}, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index ba6f51b..b705408 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1882,11 +1882,11 @@ static __initdata struct tegra_clk_init_table init_table[] = { {uartc, pll_p, 408000000, 0}, {uartd, pll_p, 408000000, 0}, {uarte, pll_p, 408000000, 0}, - {pll_a, clk_max, 564480000, 1}, - {pll_a_out0, clk_max, 11289600, 1}, - {extern1, pll_a_out0, 0, 1}, + {pll_a, clk_max, 564480000, 0}, + {pll_a_out0, clk_max, 11289600, 0}, + {extern1, pll_a_out0, 0, 0}, {clk_out_1_mux, extern1, 0, 0}, - {clk_out_1, clk_max, 0, 1}, + {clk_out_1, clk_max, 0, 0}, {blink, clk_max, 0, 1}, {i2s0, pll_a_out0, 11289600, 0}, {i2s1, pll_a_out0, 11289600, 0},