From patchwork Mon Mar 25 13:30:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 2331231 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id C7C2DDF24C for ; Mon, 25 Mar 2013 13:34:30 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UK7UO-0003Fg-N6; Mon, 25 Mar 2013 13:31:04 +0000 Received: from mail.free-electrons.com ([94.23.35.102]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UK7U0-00039T-Bn for linux-arm-kernel@lists.infradead.org; Mon, 25 Mar 2013 13:30:43 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id C34709EC; Mon, 25 Mar 2013 14:30:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 3ABAF7CF; Mon, 25 Mar 2013 14:30:39 +0100 (CET) From: Maxime Ripard To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/10] clocksource: sunxi: Cleanup the timer code Date: Mon, 25 Mar 2013 14:30:25 +0100 Message-Id: <1364218233-29636-3-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1364218233-29636-1-git-send-email-maxime.ripard@free-electrons.com> References: <1364218233-29636-1-git-send-email-maxime.ripard@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130325_093040_899922_E72BB51E X-CRM114-Status: GOOD ( 13.50 ) X-Spam-Score: -3.2 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.3 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-kernel@vger.kernel.org, John Stultz , sunny@allwinnertech.com, shuge@allwinnertech.com, Thomas Gleixner , kevin@allwinnertech.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The timer code was not exact to some aspects, since most of this code was written wihout any datasheet. Make the needed corrections to match the datasheet. Signed-off-by: Maxime Ripard --- drivers/clocksource/sunxi_timer.c | 48 ++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c index 0ce85e2..7a3ea23 100644 --- a/drivers/clocksource/sunxi_timer.c +++ b/drivers/clocksource/sunxi_timer.c @@ -25,15 +25,15 @@ #include #include -#define TIMER_CTL_REG 0x00 -#define TIMER_CTL_ENABLE (1 << 0) +#define TIMER_IRQ_EN_REG 0x00 +#define TIMER_IRQ_EN(val) (1 << val) #define TIMER_IRQ_ST_REG 0x04 -#define TIMER0_CTL_REG 0x10 -#define TIMER0_CTL_ENABLE (1 << 0) -#define TIMER0_CTL_AUTORELOAD (1 << 1) -#define TIMER0_CTL_ONESHOT (1 << 7) -#define TIMER0_INTVAL_REG 0x14 -#define TIMER0_CNTVAL_REG 0x18 +#define TIMER_CTL_REG(val) (0x10 * val + 0x10) +#define TIMER_CTL_ENABLE (1 << 0) +#define TIMER_CTL_AUTORELOAD (1 << 1) +#define TIMER_CTL_ONESHOT (1 << 7) +#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14) +#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18) #define TIMER_SCAL 16 @@ -42,21 +42,21 @@ static void __iomem *timer_base; static void sunxi_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *clk) { - u32 u = readl(timer_base + TIMER0_CTL_REG); + u32 u = readl(timer_base + TIMER_CTL_REG(0)); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - u &= ~(TIMER0_CTL_ONESHOT); - writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG); + u &= ~(TIMER_CTL_ONESHOT); + writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0)); break; case CLOCK_EVT_MODE_ONESHOT: - writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG); + writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0)); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: default: - writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG); + writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0)); break; } } @@ -64,10 +64,10 @@ static void sunxi_clkevt_mode(enum clock_event_mode mode, static int sunxi_clkevt_next_event(unsigned long evt, struct clock_event_device *unused) { - u32 u = readl(timer_base + TIMER0_CTL_REG); - writel(evt, timer_base + TIMER0_CNTVAL_REG); - writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD, - timer_base + TIMER0_CTL_REG); + u32 u = readl(timer_base + TIMER_CTL_REG(0)); + writel(evt, timer_base + TIMER_CNTVAL_REG(0)); + writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD, + timer_base + TIMER_CTL_REG(0)); return 0; } @@ -132,26 +132,26 @@ void __init sunxi_timer_init(void) rate = clk_get_rate(clk); writel(rate / (TIMER_SCAL * HZ), - timer_base + TIMER0_INTVAL_REG); + timer_base + TIMER_INTVAL_REG(0)); /* set clock source to HOSC, 16 pre-division */ - val = readl(timer_base + TIMER0_CTL_REG); + val = readl(timer_base + TIMER_CTL_REG(0)); val &= ~(0x07 << 4); val &= ~(0x03 << 2); val |= (4 << 4) | (1 << 2); - writel(val, timer_base + TIMER0_CTL_REG); + writel(val, timer_base + TIMER_CTL_REG(0)); /* set mode to auto reload */ - val = readl(timer_base + TIMER0_CTL_REG); - writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG); + val = readl(timer_base + TIMER_CTL_REG(0)); + writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0)); ret = setup_irq(irq, &sunxi_timer_irq); if (ret) pr_warn("failed to setup irq %d\n", irq); /* Enable timer0 interrupt */ - val = readl(timer_base + TIMER_CTL_REG); - writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG); + val = readl(timer_base + TIMER_IRQ_EN_REG); + writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); sunxi_clockevent.cpumask = cpumask_of(0);