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[2/2] ARM: tegra: use CS_LAR_KEY definition instead of 0xC5ACCE55

Message ID 1364235552-17851-2-git-send-email-will.deacon@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Will Deacon March 25, 2013, 6:19 p.m. UTC 
When enabling coresight on secondary cores for tegra, make use of our
fancy new definition for the magic lock code.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mach-tegra/headsmp.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Stephen Warren March 26, 2013, 8:34 p.m. UTC | #1 
On 03/25/2013 12:19 PM, Will Deacon wrote:
> When enabling coresight on secondary cores for tegra, make use of our
> fancy new definition for the magic lock code.

The code you're editing has actually been removed in the 3.10 cycle, so
there's no need for this patch any more.
diff mbox

Patch

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2..d2747fe 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,6 +1,7 @@ 
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/hardware/coresight.h>
 #include "sleep.h"
 
         .section ".text.head", "ax"
@@ -8,7 +9,7 @@ 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
 	/* Enable coresight */
-	mov32	r0, 0xC5ACCE55
+	mov32	r0, CS_LAR_KEY
 	mcr	p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)