From patchwork Tue Mar 26 10:23:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 2335681 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 9CEC5DF264 for ; Tue, 26 Mar 2013 10:26:09 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UKR2Y-00024h-Um; Tue, 26 Mar 2013 10:23:38 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UKR2U-00023U-DP for linux-arm-kernel@lists.infradead.org; Tue, 26 Mar 2013 10:23:35 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2QANWDZ031569; Tue, 26 Mar 2013 05:23:32 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2QANWkX030980; Tue, 26 Mar 2013 05:23:32 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Tue, 26 Mar 2013 05:23:32 -0500 Received: from localhost.localdomain (h56-36.vpn.ti.com [172.24.56.36]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2QANTT8026026; Tue, 26 Mar 2013 05:23:29 -0500 From: Roger Quadros To: Subject: [PATCH v2] ARM: OMAP4: clock: Add device tree support for AUXCLKs Date: Tue, 26 Mar 2013 12:23:27 +0200 Message-ID: <1364293408-20677-1-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1363703220-4777-2-git-send-email-rogerq@ti.com> References: <1363703220-4777-2-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130326_062334_543795_DFB8FDE4 X-CRM114-Status: GOOD ( 15.37 ) X-Spam-Score: -8.2 (--------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-8.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.3 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: b-cousson@ti.com, devicetree-discuss@lists.ozlabs.org, rnayak@ti.com, linux-kernel@vger.kernel.org, santosh.shilimkar@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Register a device tree clock provider for the clocks on the OMAP4 SoC. Also provide the binding information. For now we only provide AUXCLKs. Signed-off-by: Roger Quadros --- .../devicetree/bindings/clock/omap4-clock.txt | 33 ++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 5 ++ arch/arm/mach-omap2/cclock44xx_data.c | 41 ++++++++++++++++++++ 3 files changed, 79 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/omap4-clock.txt diff --git a/Documentation/devicetree/bindings/clock/omap4-clock.txt b/Documentation/devicetree/bindings/clock/omap4-clock.txt new file mode 100644 index 0000000..2845a3f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/omap4-clock.txt @@ -0,0 +1,33 @@ +* Clock bindings for Texas Instruments OMAP4 clocks + +Required properties: +- compatible: Should be "ti,omap4-clock" +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a list of OMAP4 clocks +and IDs. + + Clock ID + ------------------ + auxclk0_ck 0 + auxclk1_ck 1 + auxclk2_ck 2 + auxclk3_ck 3 + auxclk4_ck 4 + auxclk5_ck 5 + +Example: + +aux_clks: scrmclks { + compatible = "ti,omap4-clock"; + #clock-cells = <1>; +}; + +hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-supply = <&hsusb1_reset>; + clocks = <&aux_clks 3>; + clock-names = "main_clk"; + clock-frequency = <19200000>; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 739bb79..f27548a 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -101,6 +101,11 @@ ti,hwmods = "counter_32k"; }; + clks: clocks { + compatible = "ti,omap4-clock"; + #clock-cells = <1>; + }; + omap4_pmx_core: pinmux@4a100040 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a100040 0x0196>; diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 3d58f33..a93617b 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "soc.h" #include "iomap.h" @@ -1663,6 +1664,44 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), }; +/* + * List of clocks that can be referenced in device tree + * Must match with Documentation/devicetree/bindings/clock/omap4-clock.txt + */ +static struct clk *dt_clks[] = { + &auxclk0_ck, + &auxclk1_ck, + &auxclk2_ck, + &auxclk3_ck, + &auxclk4_ck, + &auxclk5_ck, +}; + +static struct clk_onecell_data clock_data; + +#ifdef CONFIG_OF +int __init omap4_clk_init_dt(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "ti,omap4-clock"); + if (np) { + clock_data.clks = dt_clks; + clock_data.clk_num = ARRAY_SIZE(dt_clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clock_data); + } + + return 0; +} + +#else + +int __init omap4_clk_init_dt(void) +{ + return 0; +} +#endif /* CONFIG_OF */ + int __init omap4xxx_clk_init(void) { u32 cpu_clkflg; @@ -1693,6 +1732,8 @@ int __init omap4xxx_clk_init(void) omap2_clk_disable_autoidle_all(); + omap4_clk_init_dt(); + /* * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power * state when turning the ABE clock domain. Workaround this by