From patchwork Wed Mar 27 11:02:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2349841 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 2D7583FC8C for ; Wed, 27 Mar 2013 11:21:20 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UKoN1-0008In-82; Wed, 27 Mar 2013 11:18:19 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UKoDE-0002fg-Qq for linux-arm-kernel@lists.infradead.org; Wed, 27 Mar 2013 11:08:14 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKB008C3G9MB6P0@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 27 Mar 2013 20:08:11 +0900 (KST) X-AuditID: cbfee61a-b7fa86d0000045ae-cd-5152d31b3b83 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 17.5B.17838.B13D2515; Wed, 27 Mar 2013 20:08:11 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKB00EJ7G19TVH0@mmp2.samsung.com>; Wed, 27 Mar 2013 20:08:11 +0900 (KST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 17/21] clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers Date: Wed, 27 Mar 2013 12:02:54 +0100 Message-id: <1364382178-25248-18-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1364382178-25248-1-git-send-email-t.figa@samsung.com> References: <1364382178-25248-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrELMWRmVeSWpSXmKPExsVy+t9jQV3py0GBBp8/KFrcWneO1aJ3wVU2 i7NNb9gt3jzczGix6fE1VosZ5/cxWaw9cpfd4umEi2wWh9+0s1qsn/GaxeLYjCWMDtwed67t YfPYvKTeo2/LKkaPz5vkAliiuGxSUnMyy1KL9O0SuDKWfDjEXHBAvuL1yllsDYz3pboYOTkk BEwkTlx/xgZhi0lcuLceyObiEBKYzihx6HkflNPFJLFl5mMWkCo2ATWJzw2PwDpEBFQlPrct YAexmQVamSQWnrcEsYUFIiQ2dF9nBrFZgGoOPGgFq+EVcJbY+WQdO8Q2eYmn9/vA5nACxd9N P8IIYgsJOEncePOUdQIj7wJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5uZsYwSH3TGoH48oG i0OMAhyMSjy8MxiCAoVYE8uKK3MPMUpwMCuJ8BodAArxpiRWVqUW5ccXleakFh9ilOZgURLn PdBqHSgkkJ5YkpqdmlqQWgSTZeLglGpg3Jbcu8jnnNFjo3lr/neEVN24uP7Q68YJLJoC20Rz 3J9U8Cumc+VM7tpxPG7u3dlydzZb6F78bcIuUzs/ZUeNVJvEv6lfbBYzHrqi9y3QwGS7487m vE4l9RN7+d9teWCotOPCYb9N5edY7vy6YrB3V6LBllfnwxsZHTjObf4n/rx2kdX9zZ0J3Eos xRmJhlrMRcWJAMx4RMU1AgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130327_070813_321721_EDAE5B95 X-CRM114-Status: UNSURE ( 7.41 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -8.2 (--------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-8.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.25 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.3 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, t.figa@samsung.com, a.hajda@samsung.com, kyungmin.park@samsung.com, thomas.abraham@linaro.org, s.nawrocki@samsung.com, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index aa8e907..c84dbc9 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -41,7 +41,7 @@ #define SRC_G3D 0xc22c #define E4210_SRC_IMAGE 0xc230 #define SRC_LCD0 0xc234 -#define SRC_LCD1 0xc238 +#define E4210_SRC_LCD1 0xc238 #define E4X12_SRC_ISP 0xc238 #define SRC_MAUDIO 0xc23c #define SRC_FSYS 0xc240 @@ -51,7 +51,7 @@ #define SRC_MASK_CAM 0xc320 #define SRC_MASK_TV 0xc324 #define SRC_MASK_LCD0 0xc334 -#define SRC_MASK_LCD1 0xc338 +#define E4210_SRC_MASK_LCD1 0xc338 #define E4X12_SRC_MASK_ISP 0xc338 #define SRC_MASK_MAUDIO 0xc33c #define SRC_MASK_FSYS 0xc340 @@ -85,7 +85,7 @@ #define GATE_IP_G3D 0xc92c #define E4210_GATE_IP_IMAGE 0xc930 #define GATE_IP_LCD0 0xc934 -#define GATE_IP_LCD1 0xc938 +#define E4210_GATE_IP_LCD1 0xc938 #define E4X12_GATE_IP_ISP 0xc938 #define E4X12_GATE_IP_MAUDIO 0xc93c #define GATE_IP_FSYS 0xc940 @@ -326,8 +326,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), - MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4), - MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4), + MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), + MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, @@ -537,10 +537,10 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), - GATE(fimd1, "fimd1", "aclk160", GATE_IP_LCD1, 0, 0, 0), - GATE(mie1, "mie1", "aclk160", GATE_IP_LCD1, 1, 0, 0), - GATE(dsim1, "dsim1", "aclk160", GATE_IP_LCD1, 3, 0, 0), - GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0), + GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), + GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), + GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), + GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, @@ -737,7 +737,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { GATE(smmu_rotator, "smmu_rotator", "aclk200", E4210_GATE_IP_IMAGE, 4, 0, 0), GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", - SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), + E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), GATE(sclk_sata, "sclk_sata", "div_sata", SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), @@ -748,7 +748,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"), GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"), GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", - SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), + E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), }; /* list of gate clocks supported in exynos4x12 soc */