From patchwork Thu Apr 4 16:37:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2394161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 2E4F73FD8C for ; Thu, 4 Apr 2013 16:43:48 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNnGM-00030r-Kd for patchwork-linux-arm@patchwork.kernel.org; Thu, 04 Apr 2013 16:43:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNnEy-0005yk-JI; Thu, 04 Apr 2013 16:42:20 +0000 Received: from mailout1.samsung.com ([203.254.224.24]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNnCU-0004DO-Tt for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2013 16:39:49 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKQ0049HOY9SGP0@mailout1.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 05 Apr 2013 01:39:45 +0900 (KST) X-AuditID: cbfee61b-b7f076d0000034b6-d4-515dacd160e9 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 3D.1B.13494.1DCAD515; Fri, 05 Apr 2013 01:39:45 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKQ00F2OOU1P170@mmp1.samsung.com>; Fri, 05 Apr 2013 01:39:45 +0900 (KST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 13/14] clocksource: samsung-time: Move IRQ mask/ack handling to the driver Date: Thu, 04 Apr 2013 18:37:10 +0200 Message-id: <1365093431-30621-14-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1365093431-30621-1-git-send-email-t.figa@samsung.com> References: <1365093431-30621-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAzWRbUhTYRTHfXZfdjcaXJfabYLhwKhAaxX2QKWWSBfRauWHCGRd9aKS07Wp ZV/czAKniUrL0eBilmJmLrc0FYscWeryZYazFy1yFNiWJgMbTWdO6dvv/P6Hcw4cAhG3oRIi v7CYVRcyBVJciNoDLjLW0ZEpP7A+GgPXGt7w4YtfAQADplEcfvLO82HXo2UcvjJ9w+BQTQJc n3dj0D7lBHCwswWD7/yx8HbTNA7buidROFbh4UOLy4lB48RLHvz8XgT9PToUPnk9x4ctMw4e nOIqUPhnZQWH9moMct4+HjQb3Si0WgwIbO9fBUmRdAfXAejKGzU47f/bAOi+e3N8etY5gNOL 4+N8mhuR09aH5fSE8T6gF+r9OF37rB3QEx4DSj93cgh91z2B015LFO3+YAJnyYvCYzlsQX4p q96fcEmYF6iwYqrupGvrlhlEC3RH9EBAUORhanzZx9viCGryixnXAyEhJpsB9aC5Fd0q9DzK 8HMSBLtwcjfl1c7jQQ4j91B39C5+kBGyCqP6G8OCvJ1UUF2BMUwPCAIlY6gFc05Qi8hkSufm kK1lu6jvX2s3xwg2/PrY780jxORJ6pbfBuqAqAmEtINwVpWt0mTlKg/GaRilpqQwNy67SGkB m//7EdkL2rXQBkgCSLeJ8moz5WKMKdWUKW2AIhBpmGiockOJcpiy66y6SKEuKWA1NhBJoNId osGbR+ViMpcpZi+zrIpV/095hECiBYU+XWPgTHXIwJq703xcEF+jY0NPhyb6hnvqa+cjriiq y5KVOxWPHR4fQ3KeKFP03qf2jOmImpSP1mjuRPH5Eee51mVZ+ky67FRGiz7RhV3ISszojJct 9a6WH8LrWId51H41vnrp7VJqWuqsROAYHq4aMIZLsp2Laa4kQ4oU1eQxsn2IWsP8A5JjTu27 AgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130404_123947_490696_9BC8CBE2 X-CRM114-Status: GOOD ( 15.97 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.24 listed in list.dnswl.org] 1.7 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -2.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: mark.rutland@arm.com, heiko@sntech.de, Tomasz Figa , tomasz.figa@gmail.com, buserror@gmail.com, jacmet@sunsite.dk, augulis.darius@gmail.com, christer@weinigel.se, sylvester.nawrocki@gmail.com, m.szyprowski@samsung.com, kgene.kim@samsung.com, linux@arm.linux.org.uk, sameo@linux.intel.com, kwangwoo.lee@gmail.com, mcuelenaere@gmail.com, arnd@arndb.de, devicetree-discuss@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org, john.stultz@linaro.org, ghcstop@gmail.com, linux@simtec.co.uk, broonie@opensource.wolfsonmicro.com, jekhor@gmail.com, kyungmin.park@samsung.com, tglx@linutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since the clocksource driver is the only user of PWM timer interrupts, there is no need to create an IRQ chip for handling them. This patch the way of PWM timer interrupt handling to use real VIC/GIC interrupt signals and handle PWM mask/ack register internally in samsung-time driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- arch/arm/mach-exynos/include/mach/irqs.h | 3 +-- arch/arm/mach-s3c24xx/include/mach/irqs.h | 6 ++++++ arch/arm/mach-s3c64xx/common.c | 3 --- arch/arm/mach-s3c64xx/include/mach/irqs.h | 8 -------- arch/arm/mach-s5p64x0/include/mach/irqs.h | 2 -- arch/arm/mach-s5pc100/include/mach/irqs.h | 2 -- arch/arm/mach-s5pv210/include/mach/irqs.h | 2 -- arch/arm/plat-samsung/devs.c | 20 ++++++++++---------- arch/arm/plat-samsung/include/plat/irqs.h | 9 --------- arch/arm/plat-samsung/s5p-irq.c | 2 -- drivers/clocksource/samsung-time.c | 10 ++++++++++ 11 files changed, 27 insertions(+), 40 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 35fe6d5..6fbe229 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -464,10 +464,9 @@ #define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16) #define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) -#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) /* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) +#define NR_IRQS (IRQ_GPIO_END + 64) #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h index 43cada8..1ecbadb 100644 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h @@ -207,6 +207,12 @@ #define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 #define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 +#define IRQ_TIMER0_VIC IRQ_TIMER0 +#define IRQ_TIMER1_VIC IRQ_TIMER1 +#define IRQ_TIMER2_VIC IRQ_TIMER2 +#define IRQ_TIMER3_VIC IRQ_TIMER3 +#define IRQ_TIMER4_VIC IRQ_TIMER4 + #ifdef CONFIG_CPU_S3C2440 #define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 #else diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 526b45e..5dca83a 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -198,9 +198,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) /* initialise the pair of VICs */ vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); - - /* add the timer sub-irqs */ - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } #define eint_offset(irq) ((irq) - IRQ_EINT(0)) diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 96d60e0..67bbd1d 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -107,14 +107,6 @@ #define IRQ_TC IRQ_PENDN #define IRQ_ADC S3C64XX_IRQ_VIC1(31) -#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) - -#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) -#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) -#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) -#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) -#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) - /* compatibility for device defines */ #define IRQ_IIC1 IRQ_S3C6410_IIC1 diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h index 5b845e8..53982db 100644 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h @@ -141,8 +141,6 @@ #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) -#define IRQ_TIMER_BASE (11) - /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 2870f12..d2eb475 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -97,8 +97,6 @@ #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) #define IRQ_VIC_END S5P_IRQ_VIC2(31) -#define IRQ_TIMER_BASE (11) - #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index e777e01..5e0de3a 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -118,8 +118,6 @@ #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) #define IRQ_VIC_END S5P_IRQ_VIC3(31) -#define IRQ_TIMER_BASE (11) - #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 747763d..cdeaf26 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -1161,20 +1161,20 @@ arch_initcall(s5p_pmu_init); */ struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, + [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0_VIC) }, + [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1_VIC) }, + [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2_VIC) }, + [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3_VIC) }, + [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4_VIC) }, }; #endif /* CONFIG_SAMSUNG_DEV_PWM */ static struct resource samsung_pwm_resource[] = { - DEFINE_RES_IRQ(IRQ_TIMER0), - DEFINE_RES_IRQ(IRQ_TIMER1), - DEFINE_RES_IRQ(IRQ_TIMER2), - DEFINE_RES_IRQ(IRQ_TIMER3), - DEFINE_RES_IRQ(IRQ_TIMER4), + DEFINE_RES_IRQ(IRQ_TIMER0_VIC), + DEFINE_RES_IRQ(IRQ_TIMER1_VIC), + DEFINE_RES_IRQ(IRQ_TIMER2_VIC), + DEFINE_RES_IRQ(IRQ_TIMER3_VIC), + DEFINE_RES_IRQ(IRQ_TIMER4_VIC), DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K), }; diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h index df46b77..039001c 100644 --- a/arch/arm/plat-samsung/include/plat/irqs.h +++ b/arch/arm/plat-samsung/include/plat/irqs.h @@ -44,15 +44,6 @@ #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) -#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x)) - -#define IRQ_TIMER0 S5P_TIMER_IRQ(0) -#define IRQ_TIMER1 S5P_TIMER_IRQ(1) -#define IRQ_TIMER2 S5P_TIMER_IRQ(2) -#define IRQ_TIMER3 S5P_TIMER_IRQ(3) -#define IRQ_TIMER4 S5P_TIMER_IRQ(4) -#define IRQ_TIMER_COUNT (5) - #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ : ((x) - 16 + S5P_EINT_BASE2)) diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c index 103e371..ce8564d 100644 --- a/arch/arm/plat-samsung/s5p-irq.c +++ b/arch/arm/plat-samsung/s5p-irq.c @@ -29,6 +29,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) for (irq = 0; irq < num_vic; irq++) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); #endif - - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } diff --git a/drivers/clocksource/samsung-time.c b/drivers/clocksource/samsung-time.c index 9425955..d9a3d60 100644 --- a/drivers/clocksource/samsung-time.c +++ b/drivers/clocksource/samsung-time.c @@ -135,6 +135,11 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; + if (pwm->variant.has_tint_cstat) { + u32 mask = (1 << timer_source.event_id); + writel(mask | (mask << 5), S3C64XX_TINT_CSTAT); + } + evt->event_handler(evt); return IRQ_HANDLED; @@ -168,6 +173,11 @@ static void __init samsung_clockevent_init(void) irq_number = pwm->irq[timer_source.event_id]; setup_irq(irq_number, &samsung_clock_event_irq); + + if (pwm->variant.has_tint_cstat) { + u32 mask = (1 << timer_source.event_id); + writel(mask | (mask << 5), S3C64XX_TINT_CSTAT); + } } static void __iomem *samsung_timer_reg(void)