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[69.228.93.79]) by mx.google.com with ESMTPS id z8sm1394888pbt.23.2013.04.10.15.03.13 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 10 Apr 2013 15:03:15 -0700 (PDT) From: Mike Turquette To: Emilio Lopez Subject: [PATCH v2 3/3] clk: sunxi: Unify oscillator clock Date: Wed, 10 Apr 2013 15:02:57 -0700 Message-Id: <1365631378-16103-4-git-send-email-mturquette@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365631378-16103-1-git-send-email-mturquette@linaro.org> References: <1365515284-32061-2-git-send-email-emilio@elopez.com.ar> <1365631378-16103-1-git-send-email-mturquette@linaro.org> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkB0Riglw1QLANyIujz409PJx1aRfPcIlxnBW4Tz3CYHAGay5yxc++bcBeEoyIGlhkCHdxZ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130410_180318_184058_B406A4E5 X-CRM114-Status: GOOD ( 14.36 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.50 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Gregory CLEMENT , Maxime Ripard , Prashant Gaikwad , Mike Turquette , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Emilio López This commit uses the new fixed-rate support on the composite clock to unify osc24M_fixed and osc24M clocks, so it matches the actual hardware. Signed-off-by: Emilio López Signed-off-by: Mike Turquette [mturquette@linaro.org: replace clk_register_gatable_osc with a call to clk_register_composite] Tested-by: Emilio López --- Emilio, I haven't been able to test these changes at run-time. Can you see if they are valid for solving your issue on sunxi? drivers/clk/sunxi/clk-sunxi.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 0bb0eb4..8492ad1 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -33,16 +33,36 @@ static DEFINE_SPINLOCK(clk_lock); static void __init sunxi_osc_clk_setup(struct device_node *node) { struct clk *clk; + struct clk_fixed_rate *fixed; + struct clk_gate *gate; const char *clk_name = node->name; - const char *parent; - void *reg; + u32 rate; - reg = of_iomap(node, 0); + /* allocate fixed-rate and gate clock structs */ + fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); + if (!fixed) + return; + gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); + if (!gate) { + kfree(fixed); + return; + } - parent = of_clk_get_parent_name(node, 0); + if (of_property_read_u32(node, "clock-frequency", &rate)) + return; + + /* set up gate and fixed rate properties */ + gate->reg = of_iomap(node, 0); + gate->bit_idx = SUNXI_OSC24M_GATE; + gate->lock = &clk_lock; + fixed->fixed_rate = rate; - clk = clk_register_gate(NULL, clk_name, parent, 0, reg, - SUNXI_OSC24M_GATE, 0, &clk_lock); + clk = clk_register_composite(NULL, clk_name, + NULL, 0, + NULL, NULL, + &fixed->hw, &clk_fixed_rate_ops, + &gate->hw, &clk_gate_ops, + CLK_IS_ROOT); if (clk) { of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -380,7 +400,6 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, /* Matches for of_clk_init */ static const __initconst struct of_device_id clk_match[] = { - {.compatible = "fixed-clock", .data = of_fixed_clk_setup,}, {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,}, {} };