From patchwork Fri Apr 12 19:17:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2437811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id B090F3FD40 for ; Fri, 12 Apr 2013 19:58:55 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQjWY-0004kn-M9; Fri, 12 Apr 2013 19:20:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQjVj-0002Qz-Ii; Fri, 12 Apr 2013 19:19:47 +0000 Received: from mailout4.samsung.com ([203.254.224.34]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQjV0-0002NB-KW for linux-arm-kernel@lists.infradead.org; Fri, 12 Apr 2013 19:19:04 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0ML50028APNPGV20@mailout4.samsung.com> for linux-arm-kernel@lists.infradead.org; Sat, 13 Apr 2013 04:19:01 +0900 (KST) X-AuditID: cbfee61a-b7fa86d0000045ae-ae-51685e252124 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 7D.F7.17838.52E58615; Sat, 13 Apr 2013 04:19:01 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0ML500CT6PL8T090@mmp2.samsung.com>; Sat, 13 Apr 2013 04:19:01 +0900 (KST) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 09/14] clocksource: samsung-pwm: Move IRQ mask/ack handling to the driver Date: Fri, 12 Apr 2013 21:17:25 +0200 Message-id: <1365794250-14436-10-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1365794250-14436-1-git-send-email-t.figa@samsung.com> References: <1365794250-14436-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsVy+t9jQV3VuIxAg5tLZS3+TjrGbrH37T9G i3+zT7FZ3Pr8iN1i48qPbBYHZj9ktTjaY2fx/9FrVovTl64xWhxct5TV4sxvXYveBVfZLFZs vcBicbbpDbvFpsfXWC1mnN/HZHH7Mq/F722NLBZrj9xlt1h6/SKTxaV5TSwW3799Y7OY93kn k8X6Ga9ZLDZvmspssWrXH0YHKY8189YwerQ097B5/P41idFj56y77B53ru1h83h37hy7x+Yl 9R7nZyxk9Hg58TebR9+WVYwe599MZfHYfm0es8e01+fZPD5vkvN4fWM2YwB/FJdNSmpOZllq kb5dAlfG3YZbjAXHHCo6tv5ha2DsN+9i5OCQEDCRWNCY3sXICWSKSVy4t54NxBYSmM4o0TRB rIuRC8juYpJYcmgzK0iCTUBN4nPDI7AiEQENiSldj9lBipgFPrFIbPw3BSwhLBAnce7pFnaQ BSwCqhITVgaDhHkFnCWebXvACLFMXuLp/T6wck6g+OS7z6AWO0n0b+xnnMDIu4CRYRWjaGpB ckFxUnquoV5xYm5xaV66XnJ+7iZGcLQ9k9rBuLLB4hCjAAejEg/vAZmMQCHWxLLiytxDjBIc zEoivDF70wKFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8x5otQ4UEkhPLEnNTk0tSC2CyTJxcEo1 MC68cPef3tVDE4NXtzp9+6JbE3vT5XttpcykN8zvt6zev9b2t8dBUdY7PX97fL6ueaobtEVR ef6EQ6rTXT/tbF/4o0Zk8vXNsadOWGsnvL26zN5/8jbBZoYDp4W69MoXX11lruH/waaitntl +6MJXbxzrRa99hVdI/vX8VKShOFRa4EsTY9o7iVKLMUZiYZazEXFiQAwzCBcsgIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130412_151903_213957_0FA0FC5B X-CRM114-Status: GOOD ( 16.08 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.34 listed in list.dnswl.org] 1.7 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -2.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: mark.rutland@arm.com, heiko@sntech.de, Tomasz Figa , tomasz.figa@gmail.com, buserror@gmail.com, jacmet@sunsite.dk, augulis.darius@gmail.com, christer@weinigel.se, sylvester.nawrocki@gmail.com, m.szyprowski@samsung.com, kgene.kim@samsung.com, linux@arm.linux.org.uk, kwangwoo.lee@gmail.com, mcuelenaere@gmail.com, arnd@arndb.de, devicetree-discuss@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org, john.stultz@linaro.org, ghcstop@gmail.com, linux@simtec.co.uk, broonie@opensource.wolfsonmicro.com, jekhor@gmail.com, kyungmin.park@samsung.com, tglx@linutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since the clocksource driver is the only user of PWM timer interrupts, there is no need to create an IRQ chip for handling them. This patch changes the way of PWM timer interrupt handling to use real VIC/GIC interrupt requests and handle PWM mask/ack register internally in samsung-pwm clocksource driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- arch/arm/mach-exynos/include/mach/irqs.h | 3 +-- arch/arm/mach-s3c24xx/include/mach/irqs.h | 6 ++++++ arch/arm/mach-s3c64xx/common.c | 3 --- arch/arm/mach-s3c64xx/include/mach/irqs.h | 8 -------- arch/arm/mach-s5p64x0/include/mach/irqs.h | 2 -- arch/arm/mach-s5pc100/include/mach/irqs.h | 2 -- arch/arm/mach-s5pv210/include/mach/irqs.h | 2 -- arch/arm/plat-samsung/devs.c | 20 ++++++++++---------- arch/arm/plat-samsung/include/plat/irqs.h | 9 --------- arch/arm/plat-samsung/s5p-irq.c | 2 -- drivers/clocksource/samsung_pwm.c | 10 ++++++++++ 11 files changed, 27 insertions(+), 40 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 35fe6d5..6fbe229 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -464,10 +464,9 @@ #define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16) #define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) -#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) /* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) +#define NR_IRQS (IRQ_GPIO_END + 64) #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h index b6dd4cb..287545f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h @@ -205,6 +205,12 @@ #define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 #define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 +#define IRQ_TIMER0_VIC IRQ_TIMER0 +#define IRQ_TIMER1_VIC IRQ_TIMER1 +#define IRQ_TIMER2_VIC IRQ_TIMER2 +#define IRQ_TIMER3_VIC IRQ_TIMER3 +#define IRQ_TIMER4_VIC IRQ_TIMER4 + #ifdef CONFIG_CPU_S3C2440 #define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 #else diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 89d2823..4cb9afe6 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -198,9 +198,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) /* initialise the pair of VICs */ vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); - - /* add the timer sub-irqs */ - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } #define eint_offset(irq) ((irq) - IRQ_EINT(0)) diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 96d60e0..67bbd1d 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -107,14 +107,6 @@ #define IRQ_TC IRQ_PENDN #define IRQ_ADC S3C64XX_IRQ_VIC1(31) -#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) - -#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) -#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) -#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) -#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) -#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) - /* compatibility for device defines */ #define IRQ_IIC1 IRQ_S3C6410_IIC1 diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h index 5b845e8..53982db 100644 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h @@ -141,8 +141,6 @@ #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) -#define IRQ_TIMER_BASE (11) - /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 2870f12..d2eb475 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -97,8 +97,6 @@ #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) #define IRQ_VIC_END S5P_IRQ_VIC2(31) -#define IRQ_TIMER_BASE (11) - #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index e777e01..5e0de3a 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -118,8 +118,6 @@ #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) #define IRQ_VIC_END S5P_IRQ_VIC3(31) -#define IRQ_TIMER_BASE (11) - #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index fbfabd2..68b163a 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -1162,20 +1162,20 @@ arch_initcall(s5p_pmu_init); */ struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, + [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0_VIC) }, + [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1_VIC) }, + [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2_VIC) }, + [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3_VIC) }, + [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4_VIC) }, }; #endif /* CONFIG_SAMSUNG_DEV_PWM */ static struct resource samsung_pwm_resource[] = { - DEFINE_RES_IRQ(IRQ_TIMER0), - DEFINE_RES_IRQ(IRQ_TIMER1), - DEFINE_RES_IRQ(IRQ_TIMER2), - DEFINE_RES_IRQ(IRQ_TIMER3), - DEFINE_RES_IRQ(IRQ_TIMER4), + DEFINE_RES_IRQ(IRQ_TIMER0_VIC), + DEFINE_RES_IRQ(IRQ_TIMER1_VIC), + DEFINE_RES_IRQ(IRQ_TIMER2_VIC), + DEFINE_RES_IRQ(IRQ_TIMER3_VIC), + DEFINE_RES_IRQ(IRQ_TIMER4_VIC), DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K), }; diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h index df46b77..039001c 100644 --- a/arch/arm/plat-samsung/include/plat/irqs.h +++ b/arch/arm/plat-samsung/include/plat/irqs.h @@ -44,15 +44,6 @@ #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) -#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x)) - -#define IRQ_TIMER0 S5P_TIMER_IRQ(0) -#define IRQ_TIMER1 S5P_TIMER_IRQ(1) -#define IRQ_TIMER2 S5P_TIMER_IRQ(2) -#define IRQ_TIMER3 S5P_TIMER_IRQ(3) -#define IRQ_TIMER4 S5P_TIMER_IRQ(4) -#define IRQ_TIMER_COUNT (5) - #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ : ((x) - 16 + S5P_EINT_BASE2)) diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c index 103e371..ce8564d 100644 --- a/arch/arm/plat-samsung/s5p-irq.c +++ b/arch/arm/plat-samsung/s5p-irq.c @@ -29,6 +29,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) for (irq = 0; irq < num_vic; irq++) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); #endif - - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } diff --git a/drivers/clocksource/samsung_pwm.c b/drivers/clocksource/samsung_pwm.c index bddf9aa..3219ecc 100644 --- a/drivers/clocksource/samsung_pwm.c +++ b/drivers/clocksource/samsung_pwm.c @@ -509,6 +509,11 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; + if (pwm->variant.has_tint_cstat) { + u32 mask = (1 << timer_source.event_id); + writel(mask | (mask << 5), S3C64XX_TINT_CSTAT); + } + evt->event_handler(evt); return IRQ_HANDLED; @@ -545,6 +550,11 @@ static void __init samsung_clockevent_init(void) irq_number = pwm->irq[timer_source.event_id]; setup_irq(irq_number, &samsung_clock_event_irq); + + if (pwm->variant.has_tint_cstat) { + u32 mask = (1 << timer_source.event_id); + writel(mask | (mask << 5), S3C64XX_TINT_CSTAT); + } } static void __iomem *samsung_timer_reg(void)