From patchwork Fri Apr 26 08:13:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 2491301 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 6ABCE3FC64 for ; Fri, 26 Apr 2013 08:14:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UVdna-0008EM-LV; Fri, 26 Apr 2013 08:14:30 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UVdnR-0004gR-IV; Fri, 26 Apr 2013 08:14:21 +0000 Received: from smtp6-v.fe.bosch.de ([2a03:cc00:ff0:100::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UVdnL-0004fL-Go for linux-arm-kernel@lists.infradead.org; Fri, 26 Apr 2013 08:14:17 +0000 Received: from vsmta14.fe.internet.bosch.com (unknown [10.4.98.54]) by imta23.fe.bosch.de (Postfix) with ESMTP id D014115801A6 for ; Fri, 26 Apr 2013 10:14:04 +0200 (CEST) Received: from localhost (vsgw4.fe.internet.bosch.com [10.4.98.12]) by vsmta14.fe.internet.bosch.com (Postfix) with SMTP id C8527A40F48 for ; Fri, 26 Apr 2013 10:14:04 +0200 (CEST) Received: from SI-HUB1000.de.bosch.com (10.4.103.106) by fe-hub01.de.bosch.com (10.3.153.37) with Microsoft SMTP Server (TLS) id 8.3.298.1; Fri, 26 Apr 2013 10:14:01 +0200 Received: from hi-z5661.hi.de.bosch.com (10.34.217.143) by SI-HUB1000.de.bosch.com (10.4.103.106) with Microsoft SMTP Server id 14.3.123.3; Fri, 26 Apr 2013 10:14:01 +0200 Received: from hi-z5661.hi.de.bosch.com (localhost [127.0.0.1]) by hi-z5661.hi.de.bosch.com (Postfix) with ESMTP id 042CB40E4C; Fri, 26 Apr 2013 10:14:01 +0200 (CEST) From: Dirk Behme To: Subject: [PATCH 2/2] ARM: i.MX6: add i.MX6 specific L2 cache configuration Date: Fri, 26 Apr 2013 10:13:56 +0200 Message-ID: <1366964036-17275-2-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 1.8.2 In-Reply-To: <1366964036-17275-1-git-send-email-dirk.behme@de.bosch.com> References: <1366964036-17275-1-git-send-email-dirk.behme@de.bosch.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130426_041415_939581_63F833D0 X-CRM114-Status: GOOD ( 11.83 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Dirk Behme , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme CC: Shawn Guo [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1 --- arch/arm/mach-imx/mach-imx6q.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 9ffd103..cdaeab5 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -281,9 +281,43 @@ static void __init imx6q_map_io(void) imx_scu_map_io(); } -static void __init imx6q_init_irq(void) +#ifdef CONFIG_CACHE_L2X0 +static void __init imx6q_init_l2cache(void) { + void __iomem *l2x0_base; + struct device_node *np; + unsigned int val; + + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); + if (!np) + goto out; + + l2x0_base = of_iomap(np, 0); + if (!l2x0_base) { + of_node_put(np); + goto out; + } + + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); + val |= 0x70800000; + writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); + val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; + writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); + + iounmap(l2x0_base); + of_node_put(np); + +out: l2x0_of_init(0, ~0UL); +} +#else +static inline void imx6q_init_l2cache(void) {} +#endif + +static void __init imx6q_init_irq(void) +{ + imx6q_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init();