From patchwork Mon May 6 20:39:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 2525151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 0AC54DF230 for ; Mon, 6 May 2013 20:39:45 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UZSCA-0000nA-CM; Mon, 06 May 2013 20:39:38 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UZSC7-00042Y-P4; Mon, 06 May 2013 20:39:35 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UZSC6-00041b-0h for linux-arm-kernel@lists.infradead.org; Mon, 06 May 2013 20:39:34 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 8ABF96665; Mon, 6 May 2013 14:43:30 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 2DE3DE40FD; Mon, 6 May 2013 14:39:09 -0600 (MDT) From: Stephen Warren To: Thierry Reding Subject: [PATCH] ARM: tegra: disable LP2 cpuidle state if PCIe is enabled Date: Mon, 6 May 2013 14:39:04 -0600 Message-Id: <1367872744-25002-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.97.7 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130506_163934_143956_D228EBE4 X-CRM114-Status: GOOD ( 15.20 ) X-Spam-Score: -3.1 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Jay Agarwal , linux-tegra@vger.kernel.org, Stephen Warren , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren Tegra20 HW appears to have a bug such that PCIe device interrupts, whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around this, simply disable LP2 if the PCI driver and DT node are both enabled. Signed-off-by: Stephen Warren --- Thierry, This patch is physically based on next-20130506 so that it doesn't conflict with any of the recent cpuidle cleanup work. I'm sending it with the expectation that you'll apply it to your PCIe development branch though. If you do that, you'll see some conflicts unless you rebase your dev branch onto something more recent than next-20130422; I assume you'll do that rebase soon enough anyway, but if you weren't planning to, I can resend the patch based on your current dev branch. arch/arm/mach-tegra/cpuidle-tegra20.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 0cdba8d..d2c9349 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -212,10 +213,39 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, } #endif +static const struct of_device_id pcie_matches[] __initconst = { + { .compatible = "nvidia,tegra20-pcie" }, + { } +}; + +/* + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether + * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around + * this, simply disable LP2 if the PCI driver and DT node are both enabled. + */ +static void __init tegra20_cpuidle_disable_lp2_with_pcie(void) +{ + struct device_node *np; + + if (!IS_ENABLED(CONFIG_PCI_TEGRA)) + return; + + np = of_find_matching_node(NULL, pcie_matches); + if (!np) + return; + + if (!of_device_is_available(np)) + return; + + pr_info("Disabling LP2 cpuidle state, since PCIe is enabled\n"); + tegra_idle_driver.state_count = 1; +} + int __init tegra20_cpuidle_init(void) { #ifdef CONFIG_PM_SLEEP tegra_tear_down_cpu = tegra20_tear_down_cpu; #endif + tegra20_cpuidle_disable_lp2_with_pcie(); return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); }