| Message ID | 1368010660-31465-3-git-send-email-jagarwal@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05/08/2013 04:57 AM, Jay Agarwal wrote: > - Add interrupt-names property > - Correct downstream I/O size > - Correct cml clock name for Tegra30 > - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next > - and should be applied on top of this. Another change that needs to be made to this file (probably as a separate change that Thierry can squash into one of his earlier changes) is to move the pcie-controller node; it is currently not in the correct place in the .dtsi file; it's not sorted by reg addresss. > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>, > <&tegra_car 118>, <&tegra_car 215>; > - clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; > + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml0"; You could drop that change if the driver named the clock "cml" rather than "cml0", which as I explained in my previous email seems like a good idea anyway. Applying the same reasoning, I wonder if for Tegra 20 too, the PCIe driver shouldn't expect clock names of just "xclk" and "pll" rather than "pcie_xclk" and "pll_e".
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 5a270ff..289ef93 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -124,7 +124,7 @@ reg-names = "pads", "afi", "cs"; interrupts = <0 98 0x04 /* controller interrupt */ 0 99 0x04>; /* MSI interrupt */ - + interrupt-names = "intr", "msi"; bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; @@ -132,13 +132,13 @@ ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */ 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>, <&tegra_car 118>, <&tegra_car 215>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml0"; status = "disabled"; pci@1,0 {
- Add interrupt-names property - Correct downstream I/O size - Correct cml clock name for Tegra30 - Patch is based on remotes/gitorious_thierryreding_linux/tegra/next - and should be applied on top of this. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> --- arch/arm/boot/dts/tegra30.dtsi | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)