From patchwork Thu May 9 05:53:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 2543201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 73BDD3FD4E for ; Thu, 9 May 2013 05:55:16 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UaJos-0003S1-3F; Thu, 09 May 2013 05:55:10 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UaJop-0007gO-CS; Thu, 09 May 2013 05:55:07 +0000 Received: from mail-pb0-x232.google.com ([2607:f8b0:400e:c01::232]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UaJom-0007fy-RQ for linux-arm-kernel@lists.infradead.org; Thu, 09 May 2013 05:55:05 +0000 Received: by mail-pb0-f50.google.com with SMTP id um15so1725650pbc.23 for ; Wed, 08 May 2013 22:54:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=E8B62BHC/Vrq+KzOZz5RWGHXbFo8+BdJDC85dbgBK2w=; b=FPpVH1xDMiJn4iB6eJpS/SGE23ZhER7tZJY+ZogijrSV+i/AjovlfiRsmmYgWWQrM+ FeMtD18lzFqJbxW5U8C1/r4kOirLzc0TM47Jtk+NSXg+vXM+3djjWxlGVHH0gExbSmWO +QrN18G9Z8fdNSldF97P/xkHfO8W1llt48gIaphWdIDwPg82IA/CO4Kn8LiDZuHdS4hg iMaW3ogdV/4tD8jyxu2Md4nZnJrQKP2jFopuUpYrkQcdNxnRepvvcZ2X474PODsuE7ri RZsYQTVw5yBrDurivGJ2ocozG+uCOTBO++/JrwRW7WSmk35ODSHCd7fL/GotpWjb9wjy xK/g== X-Received: by 10.66.162.229 with SMTP id yd5mr11518704pab.46.1368078881987; Wed, 08 May 2013 22:54:41 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.72.18.82]) by mx.google.com with ESMTPSA id yp2sm2208179pab.10.2013.05.08.22.54.38 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 May 2013 22:54:41 -0700 (PDT) From: Anup Patel To: kvmarm@lists.cs.columbia.edu Subject: [PATCH] arm64: KVM: Add bits for specifying memory type in stage2 PTE Date: Thu, 9 May 2013 11:23:33 +0530 Message-Id: <1368078813-16904-1-git-send-email-anup.patel@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQn1DGrFofVF6VeF3GuSOMU8oOiKdRsg70KNg5QXsLekoVy60bj9pbCWY7ONIBKi3zep1cXR X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130509_015504_964733_842E36C9 X-CRM114-Status: GOOD ( 12.05 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-kernel@lists.linaro.org, Anup Patel , patches@linaro.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, Pranavkumar Sawargaonkar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org We cannot use existing stage1 PTE_ATTRINDX() macro for specifying stage2 memory type because stage1 ATTRINDX = PTE[4:2] and stage2 MEMATTR = PTE[5:2]. This patch adds bit definetions for specifying device, noncacheable, writethrough, and writeback memory types in stage2 PTE and also uses it in PAGE_S2 and PAGE_S2_DEVICE. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar --- arch/arm64/include/asm/pgtable-hwdef.h | 4 ++++ arch/arm64/include/asm/pgtable.h | 6 ++++-- arch/arm64/mm/mmu.c | 9 +++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index c49cd61..555babb 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -73,6 +73,10 @@ */ #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ +#define PTE_S2_MT_DEVICE (_AT(pteval_t, 0x0) << 2) /* MemAttr[3:0] */ +#define PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */ +#define PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */ +#define PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */ /* * EL2/HYP PTE/PMD definitions diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 43ce724..3003fd0 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -60,6 +60,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define _PAGE_DEFAULT PTE_TYPE_PAGE | PTE_AF extern pgprot_t pgprot_default; +extern pgprot_t pgprot_s2; +extern pgprot_t pgprot_s2_device; #define __pgprot_modify(prot,mask,bits) \ __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) @@ -79,8 +81,8 @@ extern pgprot_t pgprot_default; #define PAGE_HYP _MOD_PROT(pgprot_default, PTE_HYP) #define PAGE_HYP_DEVICE _MOD_PROT(__pgprot(PROT_DEVICE_nGnRE), PTE_HYP) -#define PAGE_S2 _MOD_PROT(pgprot_default, PTE_S2_RDONLY) -#define PAGE_S2_DEVICE __pgprot_modify(__pgprot(PROT_DEVICE_nGnRE), PTE_PXN, PTE_S2_RDWR) +#define PAGE_S2 _MOD_PROT(pgprot_s2, PTE_USER | PTE_S2_RDONLY) +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, PTE_USER | PTE_S2_RDWR) #define __PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE) #define __PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 70b8cd4..ef26978 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -46,6 +46,12 @@ EXPORT_SYMBOL(empty_zero_page); pgprot_t pgprot_default; EXPORT_SYMBOL(pgprot_default); +pgprot_t pgprot_s2; +EXPORT_SYMBOL(pgprot_s2); + +pgprot_t pgprot_s2_device; +EXPORT_SYMBOL(pgprot_s2_device); + static pmdval_t prot_sect_kernel; struct cachepolicy { @@ -147,6 +153,9 @@ static void __init init_mem_pgprot(void) } pgprot_default = __pgprot(PTE_TYPE_PAGE | PTE_AF | default_pgprot); + + pgprot_s2 = __pgprot(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_S2_MT_WRITEBACK); + pgprot_s2_device = __pgprot(PTE_TYPE_PAGE | PTE_AF | PTE_S2_MT_DEVICE); } pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,