From patchwork Mon May 13 16:05:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Ferre X-Patchwork-Id: 2560961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 860B63FC5A for ; Mon, 13 May 2013 22:06:49 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UbvJW-0008Gp-Ht; Mon, 13 May 2013 16:09:43 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UbvFq-0000Tm-8q; Mon, 13 May 2013 16:05:38 +0000 Received: from eusmtp01.atmel.com ([212.144.249.242]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UbvFm-0000Sm-Gs for linux-arm-kernel@lists.infradead.org; Mon, 13 May 2013 16:05:35 +0000 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.30) with Microsoft SMTP Server id 14.2.342.3; Mon, 13 May 2013 18:05:05 +0200 From: Nicolas Ferre To: Jean-Christophe PLAGNIOL-VILLARD , Subject: [PATCH] net/macb: fix ISR clear-on-write behavior only for some SoC Date: Mon, 13 May 2013 18:05:05 +0200 Message-ID: <1368461105-23128-1-git-send-email-nicolas.ferre@atmel.com> X-Mailer: git-send-email 1.8.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130513_120534_798091_52FE4882 X-CRM114-Status: GOOD ( 14.59 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: netdev@vger.kernel.org, Nicolas Ferre , michal.simek@xilinx.com, linux-kernel@vger.kernel.org, Ludovic Desroches , s.trumtrar@pengutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR) introduces clear-on-write on ISR register. This behavior is not always implemented when using Cadence MACB/GEM and is breaking other platforms. We are using a new Device Tree compatibility string and a capability property to actually activate this clear-on-write behavior on ISR. Reported-by: Hein Tibosch Signed-off-by: Nicolas Ferre Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Steffen Trumtrar Acked-by: Jean-Christophe PLAGNIOL-VILLARD --- Documentation/devicetree/bindings/net/macb.txt | 2 ++ drivers/net/ethernet/cadence/macb.c | 15 +++++++++++++-- drivers/net/ethernet/cadence/macb.h | 5 +++++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 44afa0e..13ec4f6 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -6,6 +6,8 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem". + Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative + options enabled (ISR clear on write). - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: String, operation mode of the PHY interface. diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index 6be513d..628f2b0 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -485,7 +485,8 @@ static void macb_tx_interrupt(struct macb *bp) status = macb_readl(bp, TSR); macb_writel(bp, TSR, status); - macb_writel(bp, ISR, MACB_BIT(TCOMP)); + if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) + macb_writel(bp, ISR, MACB_BIT(TCOMP)); netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", (unsigned long)status); @@ -738,7 +739,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) * now. */ macb_writel(bp, IDR, MACB_RX_INT_FLAGS); - macb_writel(bp, ISR, MACB_BIT(RCOMP)); + if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) + macb_writel(bp, ISR, MACB_BIT(RCOMP)); if (napi_schedule_prep(&bp->napi)) { netdev_vdbg(bp->dev, "scheduling RX softirq\n"); @@ -1474,6 +1476,10 @@ static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,macb" }, { .compatible = "cdns,pc302-gem" }, { .compatible = "cdns,gem" }, + { + .compatible = "cdns,zynq-7000-gem", + .data = (void *)MACB_CAPS_ISR_CLEAR_ON_WRITE, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, macb_dt_ids); @@ -1484,6 +1490,7 @@ static int __init macb_probe(struct platform_device *pdev) struct macb_platform_data *pdata; struct resource *regs; struct net_device *dev; + const struct of_device_id *dev_id; struct macb *bp; struct phy_device *phydev; u32 config; @@ -1558,6 +1565,10 @@ static int __init macb_probe(struct platform_device *pdev) dev->base_addr = regs->start; + dev_id = of_match_device(macb_dt_ids, &pdev->dev); + if (dev_id) + bp->caps = (u32)dev_id->data; + /* Set MII management clock divider */ config = macb_mdc_clk_div(bp); config |= macb_dbw(bp); diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 993d703..5d622fe 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -323,6 +323,9 @@ #define MACB_MAN_READ 2 #define MACB_MAN_CODE 2 +/* Capability mask bits */ +#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x1 + /* Bit manipulation macros */ #define MACB_BIT(name) \ (1 << MACB_##name##_OFFSET) @@ -574,6 +577,8 @@ struct macb { unsigned int speed; unsigned int duplex; + u32 caps; + phy_interface_t phy_interface; /* AT91RM9200 transmit */