From patchwork Mon May 20 06:33:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjay Singh Rawat X-Patchwork-Id: 2593941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 2BFBF3FD4E for ; Mon, 20 May 2013 15:28:13 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UePH1-0006Lm-Tq; Mon, 20 May 2013 12:33:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeJfO-00058b-Ct; Mon, 20 May 2013 06:33:54 +0000 Received: from mail-da0-x22f.google.com ([2607:f8b0:400e:c00::22f]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeJfC-000561-KJ for linux-arm-kernel@lists.infradead.org; Mon, 20 May 2013 06:33:44 +0000 Received: by mail-da0-f47.google.com with SMTP id k13so3698377dae.34 for ; Sun, 19 May 2013 23:33:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=YX/SaClyOOBmxv5yj/MrHuyCEcA5J171OlFnL5GoDzE=; b=HGZI4l/7WwJdfHjyK5CD7KH8rRmS7+bNLA0TpPvV3bR2pPs27Y2y7YdgFjh3VzoS86 9iYhvY3hdmcm8Tr2u5xN1PVzOX4gWFjGQgN5miPPRoM+IdoRigUQzmOXZQKwQcW+8iyj 15PZwPFC7pr1w0mGHDaP7c9xML+io3DXOPdNFtuWzTAeF8oA4gmOQiH9hqdiV28ZpBwd uSt1LVXofq+ZfaTdAatCoarUw939cXvelVwtO2FPZIDHZxZL4cM9FJCbIpSGlfkVhJ1o fHtvzsVwUPoRl0gBpHNH3HfAW2jEwSdaDw46lECRONanZVjTQFGdyaAQnkqdSCCkTIRj 36cQ== X-Received: by 10.68.225.170 with SMTP id rl10mr16002224pbc.152.1369031600008; Sun, 19 May 2013 23:33:20 -0700 (PDT) Received: from srawat-Latitude-E6420.LGE.NET ([203.247.149.152]) by mx.google.com with ESMTPSA id ya4sm22764868pbb.24.2013.05.19.23.33.16 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 19 May 2013 23:33:19 -0700 (PDT) From: Sanjay Singh Rawat To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 1/6] ARM: cpuhotplug: move common hotplug related functions to core Date: Mon, 20 May 2013 12:03:23 +0530 Message-Id: <1369031608-27347-2-git-send-email-sanjay.rawat@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org> References: <1369031608-27347-1-git-send-email-sanjay.rawat@linaro.org> X-Gm-Message-State: ALoCoQneKf13ToTmaG7a5WXmfka4i+duqPuuDAKg6S7z+5St/MxJSmAtHC3f2I7gTCWG/0EEwxqs X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130520_023342_834304_CDB9C551 X-CRM114-Status: GOOD ( 14.66 ) X-Spam-Score: -1.1 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.8 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [203.247.149.152 listed in dnsbl.sorbs.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-dev@lists.linaro.org, linux-kernel@vger.kernel.org, Sanjay Singh Rawat X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add function which prepare arm processors to enter the low power for hotplug functionality and handle the return path. Signed-off-by: Sanjay Singh Rawat --- arch/arm/include/asm/hotplug.h | 24 +++++++++++++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cpuhotplug.c | 64 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 arch/arm/include/asm/hotplug.h create mode 100644 arch/arm/kernel/cpuhotplug.c diff --git a/arch/arm/include/asm/hotplug.h b/arch/arm/include/asm/hotplug.h new file mode 100644 index 0000000..ae80f0e --- /dev/null +++ b/arch/arm/include/asm/hotplug.h @@ -0,0 +1,24 @@ +/* + * arch/arm/include/asm/hotplug.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifdef CONFIG_HOTPLUG_CPU + +extern inline void cpu_enter_lowpower(void); +extern inline void cpu_leave_lowpower(void); + +#else +static inline void cpu_enter_lowpower(void) +{ + return -ENODEV; +} +static inline void cpu_leave_lowpower(void) +{ + return -ENODEV; +} + +#endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5f3338e..9bd370b 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o +obj-$(CONFIG_HOTPLUG_CPU) += cpuhotplug.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o diff --git a/arch/arm/kernel/cpuhotplug.c b/arch/arm/kernel/cpuhotplug.c new file mode 100644 index 0000000..8651b96 --- /dev/null +++ b/arch/arm/kernel/cpuhotplug.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +/* + * For Cortex-A9 processor + */ +static inline void ca9_enter_lowpower(void) +{ + unsigned int v; + + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %3\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +void cpu_enter_lowpower(void) +{ + int id = 0; + + /* check the cpuid */ + asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(id) : : "cc"); + + if ((id & 0xffffffff) == 0x411fc090) + ca9_enter_lowpower(); + else + pr_warn(KERN_WARNING "Unknown CPU type\n"); +}