| Message ID | 1369116149-2361-1-git-send-email-neidhard.kim@lge.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Jongsung Kim <neidhard.kim@lge.com> : > diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi > index f0052dc..1e12aef 100644 > --- a/arch/arm/boot/dts/bcm2835.dtsi > +++ b/arch/arm/boot/dts/bcm2835.dtsi > @@ -44,6 +44,7 @@ > reg = <0x7e201000 0x1000>; > interrupts = <2 25>; > clock-frequency = <3000000>; > + arm,primecell-periphid = <0x00241011>; > }; > > gpio: gpio { Stephen, how do you think about this kind of approach instead?
Have checked with the designer of the UART block and he confirmed that the 2835 PL011 contains a 16 deep fifo not 32 deep... Hardware guys, they can never just leave it alone!!! Gordon On 21 May 2013 07:07, Jongsung Kim <neidhard.kim@lge.com> wrote: > Jongsung Kim <neidhard.kim@lge.com> : >> diff --git a/arch/arm/boot/dts/bcm2835.dtsi > b/arch/arm/boot/dts/bcm2835.dtsi >> index f0052dc..1e12aef 100644 >> --- a/arch/arm/boot/dts/bcm2835.dtsi >> +++ b/arch/arm/boot/dts/bcm2835.dtsi >> @@ -44,6 +44,7 @@ >> reg = <0x7e201000 0x1000>; >> interrupts = <2 25>; >> clock-frequency = <3000000>; >> + arm,primecell-periphid = <0x00241011>; >> }; >> >> gpio: gpio { > > Stephen, how do you think about this kind of approach instead? > > > _______________________________________________ > linux-rpi-kernel mailing list > linux-rpi-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rpi-kernel
On 05/21/2013 12:02 AM, Jongsung Kim wrote: > Stephen Warren reported the recent commit 78506f2 (add support for > extended FIFO-size of PL011-r1p5) breaks the serial port on the > BCM2835 ARM SoC. > > A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. > The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep > FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for > this compatibility issue, this patch overrides the HW UART periphid > register values with the actually compatible UART periphid 0x00241011 > (r1p3 or r1p4). > > Reported-by: Stephen Warren <swarren@wwwdotorg.org> > Signed-off-by: Jongsung Kim <neidhard.kim@lge.com> I know this will work, because I tried out the same thing last week. However, I'm not convinced that it's the correct approach. What other changes exist between r1p4 and r1p5; can you check in the TRM? Faking the periphid would prevent the driver from taking account of any other changes. Should we instead add a DT property solely to override the FIFO size, and then set that for bcm2835? I guess if there really aren't any other SW-visible changes in r1p5, this approach is fine.
On 05/21/2013 10:34 AM, Stephen Warren wrote: > On 05/21/2013 12:02 AM, Jongsung Kim wrote: >> Stephen Warren reported the recent commit 78506f2 (add support for >> extended FIFO-size of PL011-r1p5) breaks the serial port on the >> BCM2835 ARM SoC. >> >> A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. >> The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep >> FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for >> this compatibility issue, this patch overrides the HW UART periphid >> register values with the actually compatible UART periphid 0x00241011 >> (r1p3 or r1p4). >> >> Reported-by: Stephen Warren <swarren@wwwdotorg.org> >> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com> > > I know this will work, because I tried out the same thing last week. > > However, I'm not convinced that it's the correct approach. What other > changes exist between r1p4 and r1p5; can you check in the TRM? Looking at the TRM, it seems this is really the only change, according to the changelog in the documentation (although it's a little difficult to tell since the document seems to have a bunch of changes that presumably don't affect behaviour). So, faking the periphid seems OK. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Let's apply for 3.10.
Stephen Warren <swarren@wwwdotorg.org> : > Looking at the TRM, it seems this is really the only change, according > to the changelog in the documentation (although it's a little difficult > to tell since the document seems to have a bunch of changes that presumably > don't affect behaviour). So, faking the periphid seems OK. > > Acked-by: Stephen Warren <swarren@wwwdotorg.org> > > Let's apply for 3.10. Thank you, Stephen.
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index f0052dc..1e12aef 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -44,6 +44,7 @@ reg = <0x7e201000 0x1000>; interrupts = <2 25>; clock-frequency = <3000000>; + arm,primecell-periphid = <0x00241011>; }; gpio: gpio {
Stephen Warren reported the recent commit 78506f2 (add support for extended FIFO-size of PL011-r1p5) breaks the serial port on the BCM2835 ARM SoC. A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for this compatibility issue, this patch overrides the HW UART periphid register values with the actually compatible UART periphid 0x00241011 (r1p3 or r1p4). Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com> --- arch/arm/boot/dts/bcm2835.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)