From patchwork Thu May 23 09:45:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 2605951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 8ABA6DFB78 for ; Thu, 23 May 2013 09:46:52 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfS6O-0004E3-AP; Thu, 23 May 2013 09:46:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfS6G-0006h7-90; Thu, 23 May 2013 09:46:20 +0000 Received: from eu1sys200aog116.obsmtp.com ([207.126.144.141]) by merlin.infradead.org with smtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfS63-0006f7-Kv for linux-arm-kernel@lists.infradead.org; Thu, 23 May 2013 09:46:08 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKUZ3lP4OcDGPvr4f0ruwYxmsr2IH1C2g8@postini.com; Thu, 23 May 2013 09:46:07 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2684211C; Thu, 23 May 2013 09:45:35 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E47142D09; Thu, 23 May 2013 09:45:19 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 1C81124C2E5; Thu, 23 May 2013 11:45:29 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.279.5; Thu, 23 May 2013 11:45:34 +0200 From: Ulf Hansson To: , Russell King Subject: [PATCH V2 2/3] mmc: mmci: Adapt to register write restrictions Date: Thu, 23 May 2013 11:45:06 +0200 Message-ID: <1369302307-28540-3-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com> References: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130523_054607_922097_3A17A647 X-CRM114-Status: GOOD ( 17.65 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.141 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Ulf Hansson , Linus Walleij , Daniel Lezcano , linux-mmc@vger.kernel.org, Rickard Andersson , Johan Rudholm , Chris Ball X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Ulf Hansson After a write to the MMCICLOCK register data cannot be written to this register for three feedback clock cycles. Writes to the MMCIPOWER register must be separated by three MCLK cycles. Previously no issues has been observered, but using higher ARM clock frequencies on STE- platforms has triggered this problem. The MMCICLOCK register is written to in .set_ios and for some data transmissions for SDIO. We do not need a delay at the data transmission path, because sending and receiving data will require more than three clock cycles. Then we use a simple logic to only delay in .set_ios and thus we don't affect throughput performance. Signed-off-by: Ulf Hansson Signed-off-by: Johan Rudholm --- Changes in v2: None --- drivers/mmc/host/mmci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 9fa8855..8f70e5b 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host, return 0; } +static void mmci_reg_delay(struct mmci_host *host) +{ + /* + * According to the spec, at least three feedback clock cycles + * of max 52 MHz must pass between two writes to the MMCICLOCK reg. + * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. + * Worst delay time during card init is at 100 kHz => 30 us. + * Worst delay time when up and running is at 25 MHz => 120 ns. + */ + if (host->cclk < 20000000) + udelay(30); + else + ndelay(120); +} + /* * This must be called with host->lock held */ @@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mmci_set_clkreg(host, ios->clock); mmci_write_pwrreg(host, pwr); + mmci_reg_delay(host); spin_unlock_irqrestore(&host->lock, flags);