From patchwork Thu May 23 13:30:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 2607011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 682A23FDBC for ; Thu, 23 May 2013 13:34:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfVdR-0006Ez-H7; Thu, 23 May 2013 13:32:50 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfVcm-00055z-Vk; Thu, 23 May 2013 13:32:08 +0000 Received: from mail.free-electrons.com ([94.23.35.102]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfVcL-00052i-Qj for linux-arm-kernel@lists.infradead.org; Thu, 23 May 2013 13:31:42 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 4A5BFE4C; Thu, 23 May 2013 15:31:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 78060742; Thu, 23 May 2013 15:31:03 +0200 (CEST) From: Thomas Petazzoni To: Andrew Lunn , Jason Cooper , Gregory Clement Subject: [PATCH v2 5/6] arm: mvebu: don't hardcode a physical address in headsmp.S Date: Thu, 23 May 2013 15:30:53 +0200 Message-Id: <1369315854-32724-6-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1369315854-32724-1-git-send-email-thomas.petazzoni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130523_093141_998016_85E0E8F8 X-CRM114-Status: GOOD ( 13.28 ) X-Spam-Score: -3.0 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Lior Amsalem , Arnd Bergmann , Maen Suleiman , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Now that the coherency_init() function is called a bit earlier, we can actually read the physical address of the coherency unit registers from the Device Tree, and communicate that to the headsmp.S code, which avoids hardcoding a physical address. Signed-off-by: Thomas Petazzoni --- arch/arm/mach-mvebu/coherency.c | 4 ++++ arch/arm/mach-mvebu/headsmp.S | 20 +++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index d74794a..3d8f40f 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -27,6 +27,7 @@ #include #include "armada-370-xp.h" +unsigned long __cpuinitdata coherency_phys_base; static void __iomem *coherency_base; static void __iomem *coherency_cpu_base; @@ -124,7 +125,10 @@ int __init coherency_init(void) np = of_find_matching_node(NULL, of_coherency_table); if (np) { + struct resource res; pr_info("Initializing Coherency fabric\n"); + of_address_to_resource(np, 0, &res); + coherency_phys_base = res.start; coherency_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 1); set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index a06e0ed..095b590 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -21,12 +21,6 @@ #include #include -/* - * At this stage the secondary CPUs don't have acces yet to the MMU, so - * we have to provide physical addresses - */ -#define ARMADA_XP_CFB_BASE 0xD0020200 - __CPUINIT /* @@ -35,15 +29,23 @@ * startup */ ENTRY(armada_xp_secondary_startup) + /* Add CPU to coherency fabric */ + adr r0, 1f + ldmia r0, {r1, r2} + sub r0, r0, r1 + add r2, r2, r0 + ldr r0, [r2] /* Read CPU id */ mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF - /* Add CPU to coherency fabric */ - ldr r0, =ARMADA_XP_CFB_BASE - bl ll_set_cpu_coherent b secondary_startup ENDPROC(armada_xp_secondary_startup) + + .align 2 +1: + .long . + .long coherency_phys_base