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[110.175.69.66]) by mx.google.com with ESMTPSA id v5sm20151586pbz.4.2013.05.25.04.09.37 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 25 May 2013 04:09:42 -0700 (PDT) From: Daniel Tang To: linux-arm-kernel@lists.infradead.org, "linux@arm.linux.org.uk ARM Linux" Subject: [RFC PATCHv4 6/6] irqchip: TI-Nspire irqchip support Date: Sat, 25 May 2013 21:08:07 +1000 Message-Id: <1369480087-24786-7-git-send-email-dt.tangr@gmail.com> X-Mailer: git-send-email 1.8.1.3 In-Reply-To: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com> References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130525_071006_011382_E05ADBA3 X-CRM114-Status: GOOD ( 20.28 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (dt.tangr[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Arnd Bergmann , Linus Walleij , linux-kernel@vger.kernel.org, "fabian@ritter-vogt.de Vogt" , Daniel Tang , Thomas Gleixner , Lionel Debroux X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add support for the interrupt controller on TI-Nspires. Signed-off-by: Daniel Tang --- .../interrupt-controller/lsi,zevio-intc.txt | 18 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-zevio.c | 177 +++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt create mode 100644 drivers/irqchip/irq-zevio.c -- 1.8.1.3 diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt new file mode 100644 index 0000000..aee38e7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt @@ -0,0 +1,18 @@ +TI-NSPIRE interrupt controller + +Required properties: +- compatible: Compatible property value should be "lsi,zevio-intc". + +- reg: Physical base address of the controller and length of memory mapped + region. + +- interrupt-controller : Identifies the node as an interrupt controller + +Example: + +interrupt-controller { + compatible = "lsi,zevio-intc"; + interrupt-controller; + reg = <0xDC000000 0x1000>; + #interrupt-cells = <1>; +}; diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index cda4cb5..f313d14 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o +obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o diff --git a/drivers/irqchip/irq-zevio.c b/drivers/irqchip/irq-zevio.c new file mode 100644 index 0000000..3101c2a --- /dev/null +++ b/drivers/irqchip/irq-zevio.c @@ -0,0 +1,177 @@ +/* + * linux/drivers/irqchip/irq-nspire-classic.c + * + * Copyright (C) 2013 Daniel Tang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "irqchip.h" + +#define IO_STATUS 0x000 +#define IO_RAW_STATUS 0x004 +#define IO_ENABLE 0x008 +#define IO_DISABLE 0x00C +#define IO_CURRENT 0x020 +#define IO_RESET 0x028 +#define IO_MAX_PRIOTY 0x02C + +#define IO_IRQ_BASE 0x000 +#define IO_FIQ_BASE 0x100 + +#define IO_INVERT_SEL 0x200 +#define IO_STICKY_SEL 0x204 +#define IO_PRIORITY_SEL 0x300 + +#define MAX_INTRS 32 +#define FIQ_START MAX_INTRS + + +static void __iomem *irq_io_base; +static struct irq_domain *nspire_irq_domain; + +static void nspire_irq_ack(struct irq_data *irqd) +{ + void __iomem *base = irq_io_base; + + if (irqd->hwirq < FIQ_START) + base += IO_IRQ_BASE; + else + base += IO_FIQ_BASE; + + readl(base + IO_RESET); +} + +static void nspire_irq_unmask(struct irq_data *irqd) +{ + void __iomem *base = irq_io_base; + int irqnr = irqd->hwirq; + + if (irqnr < FIQ_START) { + base += IO_IRQ_BASE; + } else { + irqnr -= MAX_INTRS; + base += IO_FIQ_BASE; + } + + writel((1<hwirq; + + if (irqnr < FIQ_START) { + base += IO_IRQ_BASE; + } else { + irqnr -= FIQ_START; + base += IO_FIQ_BASE; + } + + writel((1<