From patchwork Mon May 27 09:00:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 2618531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 3BD873FD4E for ; Mon, 27 May 2013 09:30:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtlS-0006De-0d; Mon, 27 May 2013 09:30:50 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtlO-0002UJ-F8; Mon, 27 May 2013 09:30:46 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtlJ-0002Td-TJ for linux-arm-kernel@lists.infradead.org; Mon, 27 May 2013 09:30:43 +0000 Received: from vergenet.net (ac225145.ppp.asahi-net.or.jp [183.77.225.145]) by kirsty.vergenet.net (Postfix) with ESMTP id 9ACEA26715F; Mon, 27 May 2013 19:00:16 +1000 (EST) Received: by vergenet.net (Postfix, from userid 7100) id 402257C1B5A; Mon, 27 May 2013 18:00:58 +0900 (JST) From: Simon Horman To: Arnd Bergmann , Olof Johansson Subject: [PATCH 7/8] ARM: shmobile: sh73a0: do not overwrite all div4 clock operations Date: Mon, 27 May 2013 18:00:51 +0900 Message-Id: <1369645252-3847-8-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au> References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130527_053042_952169_53BBBA97 X-CRM114-Status: GOOD ( 16.54 ) X-Spam-Score: -3.7 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [202.4.237.240 listed in list.dnswl.org] -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-sh@vger.kernel.org, Magnus Damm , Guennadi Liakhovetski , arm@kernel.org, Simon Horman , Guennadi Liakhovetski , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Guennadi Liakhovetski An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU frequency" intended to replace some clock operations only for the Z-clock, instead it replaced them for all div4 clocks, since all div4 clocks share the same copy of clock operations. Fix this by using a separate clock operations structure for Z-clock. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index acb9e09..d05cf90 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -257,9 +257,8 @@ static struct clk twd_clk = { .ops = &twd_clk_ops, }; -static int (*div4_set_rate)(struct clk *clk, unsigned long rate); -static unsigned long (*div4_recalc)(struct clk *clk); -static long (*div4_round_rate)(struct clk *clk, unsigned long rate); +static struct sh_clk_ops zclk_ops; +static const struct sh_clk_ops *div4_clk_ops; static int zclk_set_rate(struct clk *clk, unsigned long rate) { @@ -275,7 +274,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) /* 1:1 - switch off divider */ __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); /* nullify the divider to prepare for the next time */ - ret = div4_set_rate(clk, rate / 2); + ret = div4_clk_ops->set_rate(clk, rate / 2); if (!ret) ret = frqcr_kick(); if (ret > 0) @@ -290,7 +289,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) * set the divider - call the DIV4 method, it will kick * FRQCRB too */ - ret = div4_set_rate(clk, rate); + ret = div4_clk_ops->set_rate(clk, rate); if (ret < 0) goto esetrate; } @@ -302,7 +301,7 @@ esetrate: static long zclk_round_rate(struct clk *clk, unsigned long rate) { - unsigned long div_freq = div4_round_rate(clk, rate), + unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), parent_freq = clk_get_rate(clk->parent); if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) @@ -317,7 +316,7 @@ static unsigned long zclk_recalc(struct clk *clk) * Must recalculate frequencies in case PLL0 has been changed, even if * the divisor is unused ATM! */ - unsigned long div_freq = div4_recalc(clk); + unsigned long div_freq = div4_clk_ops->recalc(clk); if (__raw_readl(FRQCRB) & (1 << 28)) return div_freq; @@ -327,13 +326,16 @@ static unsigned long zclk_recalc(struct clk *clk) static void zclk_extend(void) { + div4_clk_ops = div4_clks[DIV4_Z].ops; + /* We extend the DIV4 clock with a 1:1 pass-through case */ - div4_set_rate = div4_clks[DIV4_Z].ops->set_rate; - div4_round_rate = div4_clks[DIV4_Z].ops->round_rate; - div4_recalc = div4_clks[DIV4_Z].ops->recalc; - div4_clks[DIV4_Z].ops->set_rate = zclk_set_rate; - div4_clks[DIV4_Z].ops->round_rate = zclk_round_rate; - div4_clks[DIV4_Z].ops->recalc = zclk_recalc; + zclk_ops = *div4_clk_ops; + + zclk_ops.set_rate = zclk_set_rate; + zclk_ops.round_rate = zclk_round_rate; + zclk_ops.recalc = zclk_recalc; + + div4_clks[DIV4_Z].ops = &zclk_ops; } enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,