From patchwork Mon May 27 09:00:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 2619151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 924963FDBC for ; Mon, 27 May 2013 11:09:26 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtSW-0003VF-Eg; Mon, 27 May 2013 09:11:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtMG-0001xu-B1; Mon, 27 May 2013 09:04:48 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtJW-0001ja-Kg for linux-arm-kernel@merlin.infradead.org; Mon, 27 May 2013 09:01:59 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UgtIM-0008Lh-AH for linux-arm-kernel@lists.infradead.org; Mon, 27 May 2013 09:00:52 +0000 Received: from vergenet.net (ac225145.ppp.asahi-net.or.jp [183.77.225.145]) by kirsty.vergenet.net (Postfix) with ESMTP id 9AE0F267161; Mon, 27 May 2013 19:00:16 +1000 (EST) Received: by vergenet.net (Postfix, from userid 7100) id 434B27C1B5B; Mon, 27 May 2013 18:00:58 +0900 (JST) From: Simon Horman To: Arnd Bergmann , Olof Johansson Subject: [PATCH 8/8] ARM: shmobile: sh73a0: div4 clocks must check the kick bit before changing rate Date: Mon, 27 May 2013 18:00:52 +0900 Message-Id: <1369645252-3847-9-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au> References: <1369645252-3847-1-git-send-email-horms+renesas@verge.net.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130527_100050_257858_12A5C801 X-CRM114-Status: GOOD ( 16.28 ) X-Spam-Score: -3.7 (---) X-Spam-Report: SpamAssassin version 3.3.2 on casper.infradead.org summary: Content analysis details: (-3.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [202.4.237.240 listed in list.dnswl.org] -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-sh@vger.kernel.org, Magnus Damm , Guennadi Liakhovetski , arm@kernel.org, Simon Horman , Guennadi Liakhovetski , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Guennadi Liakhovetski According to the datasheet, it is not allowed to change div4 clock rates if an earlier rate change operation is still in progress, as indicated by a set kick bit. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-sh73a0.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index d05cf90..d9fd033 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -257,7 +257,7 @@ static struct clk twd_clk = { .ops = &twd_clk_ops, }; -static struct sh_clk_ops zclk_ops; +static struct sh_clk_ops zclk_ops, kicker_ops; static const struct sh_clk_ops *div4_clk_ops; static int zclk_set_rate(struct clk *clk, unsigned long rate) @@ -324,18 +324,32 @@ static unsigned long zclk_recalc(struct clk *clk) return clk_get_rate(clk->parent); } -static void zclk_extend(void) +static int kicker_set_rate(struct clk *clk, unsigned long rate) { - div4_clk_ops = div4_clks[DIV4_Z].ops; + if (__raw_readl(FRQCRB) & (1 << 31)) + return -EBUSY; + + return div4_clk_ops->set_rate(clk, rate); +} + +static void div4_clk_extend(void) +{ + int i; + + div4_clk_ops = div4_clks[0].ops; + /* Add a kicker-busy check before changing the rate */ + kicker_ops = *div4_clk_ops; /* We extend the DIV4 clock with a 1:1 pass-through case */ zclk_ops = *div4_clk_ops; + kicker_ops.set_rate = kicker_set_rate; zclk_ops.set_rate = zclk_set_rate; zclk_ops.round_rate = zclk_round_rate; zclk_ops.recalc = zclk_recalc; - div4_clks[DIV4_Z].ops = &zclk_ops; + for (i = 0; i < DIV4_NR; i++) + div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops; } enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, @@ -697,7 +711,7 @@ void __init sh73a0_clock_init(void) if (!ret) { ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - zclk_extend(); + div4_clk_extend(); } if (!ret)